hw/arm: add experimental iPhone 5 A6 platform
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/*
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* Apple Interrupt Controller v2 as used by the S5L8950X.
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*
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* The A6 SecureROM uses the same register layout later documented for AICv2:
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* event acknowledge at 0x2004, per-source destinations at 0x3000 and mask
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* set/clear banks at 0x4100/0x4180.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "hw/core/sysbus.h"
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#include "hw/core/irq.h"
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#include "qom/object.h"
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#define TYPE_S5L8950X_AIC "s5l8950x-aic"
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OBJECT_DECLARE_SIMPLE_TYPE(S5L8950XAicState, S5L8950X_AIC)
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#define S5L8950X_AIC_NUM_IRQS 256
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#define S5L8950X_AIC_NUM_BANKS (S5L8950X_AIC_NUM_IRQS / 32)
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#define AIC_REV 0x0000
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#define AIC_CAP0 0x0004
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#define AIC_CAP1 0x0008
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#define AIC_RST 0x000c
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#define AIC_GLB_CFG 0x0010
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#define AIC_TIME_LO 0x0020
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#define AIC_TIME_HI 0x0028
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#define AIC_WHOAMI 0x2000
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#define AIC_ACK 0x2004
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#define AIC_IPI_SET 0x2008
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#define AIC_IPI_CLR 0x200c
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#define AIC_SRC_CFG_BASE 0x3000
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#define AIC_MASK_SET_BASE 0x4100
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#define AIC_MASK_CLR_BASE 0x4180
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#define AIC_INT_STATE_BASE 0x4200
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#define AIC_EVENT_EXT 0x00010000
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struct S5L8950XAicState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t mask[S5L8950X_AIC_NUM_BANKS];
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uint32_t pending[S5L8950X_AIC_NUM_BANKS];
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uint32_t src_cfg[S5L8950X_AIC_NUM_IRQS];
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uint32_t glb_cfg;
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qemu_irq irq;
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qemu_irq fiq;
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};
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static bool s5l8950x_aic_irq_is_active(S5L8950XAicState *s, int irq)
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{
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int bank = irq / 32;
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uint32_t bit = BIT(irq % 32);
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return (s->pending[bank] & bit) && !(s->mask[bank] & bit) &&
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(s->src_cfg[irq] & 1);
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}
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static void s5l8950x_aic_update(S5L8950XAicState *s)
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{
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bool active = false;
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int irq;
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for (irq = 0; irq < S5L8950X_AIC_NUM_IRQS; irq++) {
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if (s5l8950x_aic_irq_is_active(s, irq)) {
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active = true;
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break;
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}
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}
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qemu_set_irq(s->irq, active);
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qemu_irq_lower(s->fiq);
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}
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static uint32_t s5l8950x_aic_ack(S5L8950XAicState *s)
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{
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int irq;
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for (irq = 0; irq < S5L8950X_AIC_NUM_IRQS; irq++) {
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if (s5l8950x_aic_irq_is_active(s, irq)) {
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s->mask[irq / 32] |= BIT(irq % 32);
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s5l8950x_aic_update(s);
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return AIC_EVENT_EXT | irq;
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}
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}
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s5l8950x_aic_update(s);
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return 0;
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}
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static void s5l8950x_aic_set_irq(void *opaque, int irq, int level)
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{
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S5L8950XAicState *s = opaque;
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uint32_t bit = BIT(irq % 32);
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if (level) {
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s->pending[irq / 32] |= bit;
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} else {
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s->pending[irq / 32] &= ~bit;
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}
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s5l8950x_aic_update(s);
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}
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static uint64_t s5l8950x_aic_read(void *opaque, hwaddr offset, unsigned size)
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{
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S5L8950XAicState *s = opaque;
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uint64_t ticks;
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ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000,
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NANOSECONDS_PER_SECOND);
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switch (offset) {
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case AIC_REV:
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return 2;
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case AIC_CAP0:
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return S5L8950X_AIC_NUM_IRQS;
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case AIC_CAP1:
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return 0;
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case AIC_RST:
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return 0;
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case AIC_GLB_CFG:
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return s->glb_cfg;
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case AIC_TIME_LO:
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return (uint32_t)ticks;
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case AIC_TIME_HI:
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return (uint32_t)(ticks >> 32);
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case AIC_WHOAMI:
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return 0;
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case AIC_ACK:
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return s5l8950x_aic_ack(s);
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case AIC_SRC_CFG_BASE ... AIC_SRC_CFG_BASE +
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S5L8950X_AIC_NUM_IRQS * 4 - 4:
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return s->src_cfg[(offset - AIC_SRC_CFG_BASE) / 4];
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case AIC_MASK_SET_BASE ... AIC_MASK_SET_BASE +
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S5L8950X_AIC_NUM_BANKS * 4 - 4:
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return s->mask[(offset - AIC_MASK_SET_BASE) / 4];
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case AIC_MASK_CLR_BASE ... AIC_MASK_CLR_BASE +
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S5L8950X_AIC_NUM_BANKS * 4 - 4:
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return s->mask[(offset - AIC_MASK_CLR_BASE) / 4];
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case AIC_INT_STATE_BASE ... AIC_INT_STATE_BASE +
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S5L8950X_AIC_NUM_BANKS * 4 - 4:
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return s->pending[(offset - AIC_INT_STATE_BASE) / 4];
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented read at 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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}
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static void s5l8950x_aic_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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S5L8950XAicState *s = opaque;
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switch (offset) {
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case AIC_RST:
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memset(s->mask, 0xff, sizeof(s->mask));
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memset(s->pending, 0, sizeof(s->pending));
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s5l8950x_aic_update(s);
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break;
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case AIC_GLB_CFG:
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s->glb_cfg = value;
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break;
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case AIC_IPI_SET:
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case AIC_IPI_CLR:
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break;
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case AIC_SRC_CFG_BASE ... AIC_SRC_CFG_BASE +
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S5L8950X_AIC_NUM_IRQS * 4 - 4:
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s->src_cfg[(offset - AIC_SRC_CFG_BASE) / 4] = value;
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s5l8950x_aic_update(s);
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break;
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case AIC_MASK_SET_BASE ... AIC_MASK_SET_BASE +
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S5L8950X_AIC_NUM_BANKS * 4 - 4:
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s->mask[(offset - AIC_MASK_SET_BASE) / 4] |= value;
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s5l8950x_aic_update(s);
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break;
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case AIC_MASK_CLR_BASE ... AIC_MASK_CLR_BASE +
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S5L8950X_AIC_NUM_BANKS * 4 - 4:
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s->mask[(offset - AIC_MASK_CLR_BASE) / 4] &= ~value;
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s5l8950x_aic_update(s);
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented write at 0x%" HWADDR_PRIx
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" = 0x%08" PRIx64 "\n",
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__func__, offset, value);
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break;
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}
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}
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static const MemoryRegionOps s5l8950x_aic_ops = {
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.read = s5l8950x_aic_read,
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.write = s5l8950x_aic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void s5l8950x_aic_reset(DeviceState *dev)
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{
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S5L8950XAicState *s = S5L8950X_AIC(dev);
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memset(s->mask, 0xff, sizeof(s->mask));
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memset(s->pending, 0, sizeof(s->pending));
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memset(s->src_cfg, 0, sizeof(s->src_cfg));
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s->glb_cfg = 0;
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s5l8950x_aic_update(s);
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}
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static void s5l8950x_aic_init(Object *obj)
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{
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S5L8950XAicState *s = S5L8950X_AIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &s5l8950x_aic_ops, s,
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TYPE_S5L8950X_AIC, 0x8000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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sysbus_init_irq(sbd, &s->fiq);
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qdev_init_gpio_in(DEVICE(obj), s5l8950x_aic_set_irq,
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S5L8950X_AIC_NUM_IRQS);
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}
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static void s5l8950x_aic_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, s5l8950x_aic_reset);
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}
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static const TypeInfo s5l8950x_aic_info = {
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.name = TYPE_S5L8950X_AIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(S5L8950XAicState),
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.instance_init = s5l8950x_aic_init,
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.class_init = s5l8950x_aic_class_init,
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};
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static void s5l8950x_aic_register_types(void)
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{
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type_register_static(&s5l8950x_aic_info);
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}
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type_init(s5l8950x_aic_register_types)
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