Import QEMU upstream snapshot d2e570c
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
This commit is contained in:
+1916
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,364 @@
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/*
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* Interface to the capstone disassembler.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/bswap.h"
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#include "disas/dis-asm.h"
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#include "disas/capstone.h"
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/*
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* Temporary storage for the capstone library. This will be alloced via
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* malloc with a size private to the library; thus there's no reason not
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* to share this across calls and across host vs target disassembly.
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*/
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static __thread cs_insn *cap_insn;
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/*
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* The capstone library always skips 2 bytes for S390X.
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* This is less than ideal, since we can tell from the first two bits
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* the size of the insn and thus stay in sync with the insn stream.
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*/
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static size_t CAPSTONE_API
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cap_skipdata_s390x_cb(const uint8_t *code, size_t code_size,
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size_t offset, void *user_data)
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{
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size_t ilen;
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/* See get_ilen() in target/s390x/internal.h. */
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switch (code[offset] >> 6) {
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case 0:
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ilen = 2;
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break;
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case 1:
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case 2:
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ilen = 4;
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break;
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default:
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ilen = 6;
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break;
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}
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return ilen;
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}
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static const cs_opt_skipdata cap_skipdata_s390x = {
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.mnemonic = ".byte",
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.callback = cap_skipdata_s390x_cb
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};
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/* Similarly for RISCV */
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static size_t CAPSTONE_API
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cap_skipdata_riscv_cb(const uint8_t *code, size_t code_size,
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size_t offset, void *user_data)
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{
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/* See insn_len() from target/riscv/internals.h */
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return (code[offset] & 3) == 3 ? 4 : 2;
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}
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static const cs_opt_skipdata cap_skipdata_riscv = {
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.mnemonic = ".byte",
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.callback = cap_skipdata_riscv_cb
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};
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/*
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* Initialize the Capstone library.
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*
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* ??? It would be nice to cache this. We would need one handle for the
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* host and one for the target. For most targets we can reset specific
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* parameters via cs_option(CS_OPT_MODE, new_mode), but we cannot change
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* CS_ARCH_* in this way. Thus we would need to be able to close and
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* re-open the target handle with a different arch for the target in order
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* to handle AArch64 vs AArch32 mode switching.
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*/
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static cs_err cap_disas_start(disassemble_info *info, csh *handle)
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{
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cs_mode cap_mode = info->cap_mode;
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cs_err err;
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cap_mode += (info->endian == BFD_ENDIAN_BIG ? CS_MODE_BIG_ENDIAN
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: CS_MODE_LITTLE_ENDIAN);
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err = cs_open(info->cap_arch, cap_mode, handle);
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if (err != CS_ERR_OK) {
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return err;
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}
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/* "Disassemble" unknown insns as ".byte W,X,Y,Z". */
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cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON);
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switch (info->cap_arch) {
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case CS_ARCH_RISCV:
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cs_option(*handle, CS_OPT_SKIPDATA_SETUP,
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(uintptr_t)&cap_skipdata_riscv);
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break;
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case CS_ARCH_SYSTEMZ:
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cs_option(*handle, CS_OPT_SKIPDATA_SETUP,
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(uintptr_t)&cap_skipdata_s390x);
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break;
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case CS_ARCH_X86:
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/*
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* We don't care about errors (if for some reason the library
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* is compiled without AT&T syntax); the user will just have
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* to deal with the Intel syntax.
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*/
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cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
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break;
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}
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/* Allocate temp space for cs_disasm_iter. */
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if (cap_insn == NULL) {
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cap_insn = cs_malloc(*handle);
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if (cap_insn == NULL) {
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cs_close(handle);
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return CS_ERR_MEM;
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}
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}
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return CS_ERR_OK;
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}
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static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
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int i, int n)
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{
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fprintf_function print = info->fprintf_func;
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FILE *stream = info->stream;
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int unit = MIN(info->cap_insn_unit, n - i);
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switch (unit) {
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case 4:
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if (info->endian == BFD_ENDIAN_BIG) {
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for (; i < n; i += 4) {
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print(stream, " %08x", ldl_be_p(insn->bytes + i));
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}
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} else {
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for (; i < n; i += 4) {
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print(stream, " %08x", ldl_le_p(insn->bytes + i));
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}
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}
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break;
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case 2:
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if (info->endian == BFD_ENDIAN_BIG) {
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for (; i < n; i += 2) {
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print(stream, " %04x", lduw_be_p(insn->bytes + i));
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}
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} else {
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for (; i < n; i += 2) {
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print(stream, " %04x", lduw_le_p(insn->bytes + i));
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}
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}
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break;
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default:
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for (; i < n; i++) {
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print(stream, " %02x", insn->bytes[i]);
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}
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break;
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}
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if (unit < info->cap_insn_unit) {
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int width = (info->cap_insn_unit - unit) * 2;
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print(stream, "%*s", width, "");
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}
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}
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static void cap_dump_insn(disassemble_info *info, cs_insn *insn)
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{
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fprintf_function print = info->fprintf_func;
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FILE *stream = info->stream;
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int i, n, split;
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print(stream, "0x%08" PRIx64 ": ", insn->address);
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n = insn->size;
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split = info->cap_insn_split;
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/* Dump the first SPLIT bytes of the instruction. */
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cap_dump_insn_units(info, insn, 0, MIN(n, split));
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/* Add padding up to SPLIT so that mnemonics line up. */
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if (n < split) {
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int width = (split - n) / info->cap_insn_unit;
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width *= (2 * info->cap_insn_unit + 1);
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print(stream, "%*s", width, "");
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}
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/* Print the actual instruction. */
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print(stream, " %-8s %s\n", insn->mnemonic, insn->op_str);
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/* Dump any remaining part of the insn on subsequent lines. */
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for (i = split; i < n; i += split) {
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print(stream, "0x%08" PRIx64 ": ", insn->address + i);
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cap_dump_insn_units(info, insn, i, MIN(n, i + split));
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print(stream, "\n");
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}
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}
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/* Disassemble SIZE bytes at PC for the target. */
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bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size)
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{
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uint8_t cap_buf[1024];
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csh handle;
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cs_insn *insn;
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size_t csize = 0;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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while (1) {
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size_t tsize = MIN(sizeof(cap_buf) - csize, size);
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const uint8_t *cbuf = cap_buf;
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if (info->read_memory_func(pc + csize, cap_buf + csize, tsize, info) == 0) {
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csize += tsize;
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size -= tsize;
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while (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
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cap_dump_insn(info, insn);
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}
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/* If the target memory is not consumed, go back for more... */
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if (size != 0) {
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/*
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* ... taking care to move any remaining fractional insn
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* to the beginning of the buffer.
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*/
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if (csize != 0) {
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memmove(cap_buf, cbuf, csize);
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}
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continue;
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}
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/*
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* Since the target memory is consumed, we should not have
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* a remaining fractional insn.
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*/
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if (csize != 0) {
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info->fprintf_func(info->stream,
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"Disassembler disagrees with translator "
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"over instruction decoding\n"
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"Please report this to [email protected]\n");
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}
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break;
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} else {
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info->fprintf_func(info->stream,
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"0x%08" PRIx64 ": unable to read memory\n", pc);
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break;
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}
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble SIZE bytes at CODE for the host. */
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bool cap_disas_host(disassemble_info *info, const void *code, size_t size)
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{
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csh handle;
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const uint8_t *cbuf;
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cs_insn *insn;
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uint64_t pc;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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cbuf = code;
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pc = (uintptr_t)code;
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while (cs_disasm_iter(handle, &cbuf, &size, &pc, insn)) {
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cap_dump_insn(info, insn);
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}
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if (size != 0) {
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info->fprintf_func(info->stream,
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"Disassembler disagrees with TCG over instruction encoding\n"
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"Please report this to [email protected]\n");
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble COUNT insns at PC for the target. */
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bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
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{
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uint8_t cap_buf[32];
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csh handle;
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cs_insn *insn;
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size_t csize = 0;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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while (1) {
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/*
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* We want to read memory for one insn, but generically we do not
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* know how much memory that is. We have a small buffer which is
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* known to be sufficient for all supported targets. Try to not
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* read beyond the page, Just In Case. For even more simplicity,
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* ignore the actual target page size and use a 1k boundary. If
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* that turns out to be insufficient, we'll come back around the
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* loop and read more.
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*/
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uint64_t epc = QEMU_ALIGN_UP(pc + csize + 1, 1024);
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size_t tsize = MIN(sizeof(cap_buf) - csize, epc - pc);
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const uint8_t *cbuf = cap_buf;
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/* Make certain that we can make progress. */
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assert(tsize != 0);
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if (info->read_memory_func(pc + csize, cap_buf + csize,
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tsize, info) == 0)
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{
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csize += tsize;
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if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
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cap_dump_insn(info, insn);
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if (--count <= 0) {
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break;
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}
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}
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memmove(cap_buf, cbuf, csize);
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} else {
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info->fprintf_func(info->stream,
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"0x%08" PRIx64 ": unable to read memory\n", pc);
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break;
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}
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble a single instruction directly into plugin output */
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bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size)
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{
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uint8_t cap_buf[32];
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const uint8_t *cbuf = cap_buf;
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csh handle;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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assert(size < sizeof(cap_buf));
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info->read_memory_func(pc, cap_buf, size, info);
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if (cs_disasm_iter(handle, &cbuf, &size, &pc, cap_insn)) {
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info->fprintf_func(info->stream, "%s %s",
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cap_insn->mnemonic, cap_insn->op_str);
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}
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cs_close(&handle);
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return true;
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}
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@@ -0,0 +1,99 @@
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/*
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* Common routines for disassembly.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "disas/disas.h"
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#include "disas/capstone.h"
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#include "hw/core/cpu.h"
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#include "disas-internal.h"
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/* Filled in by elfload.c. Simplistic, but will do for now. */
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struct syminfo *syminfos = NULL;
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/*
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* Print an error message. We can assume that this is in response to
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* an error return from {host,target}_read_memory.
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*/
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static void perror_memory(int status, bfd_vma memaddr,
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struct disassemble_info *info)
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{
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if (status != EIO) {
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/* Can't happen. */
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info->fprintf_func(info->stream, "Unknown error %d\n", status);
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} else {
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/* Address between memaddr and memaddr + len was out of bounds. */
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info->fprintf_func(info->stream,
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"Address 0x%" PRIx64 " is out of bounds.\n",
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memaddr);
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}
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}
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/* Print address in hex. */
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static void print_address(bfd_vma addr, struct disassemble_info *info)
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{
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info->fprintf_func(info->stream, "0x%" PRIx64, addr);
|
||||
}
|
||||
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||||
/* Stub prevents some fruitless earching in optabs disassemblers. */
|
||||
static int symbol_at_address(bfd_vma addr, struct disassemble_info *info)
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{
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return 1;
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}
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void disas_initialize_debug(CPUDebug *s)
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{
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memset(s, 0, sizeof(*s));
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s->info.arch = bfd_arch_unknown;
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s->info.cap_arch = -1;
|
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s->info.cap_insn_unit = 4;
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||||
s->info.cap_insn_split = 4;
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||||
s->info.memory_error_func = perror_memory;
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||||
s->info.symbol_at_address_func = symbol_at_address;
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||||
}
|
||||
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||||
void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
|
||||
{
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||||
disas_initialize_debug(s);
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||||
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||||
s->cpu = cpu;
|
||||
s->info.print_address_func = print_address;
|
||||
s->info.endian = BFD_ENDIAN_UNKNOWN;
|
||||
|
||||
if (cpu->cc->disas_set_info) {
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||||
cpu->cc->disas_set_info(cpu, &s->info);
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||||
g_assert(s->info.endian != BFD_ENDIAN_UNKNOWN);
|
||||
}
|
||||
}
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||||
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||||
int disas_gstring_printf(FILE *stream, const char *fmt, ...)
|
||||
{
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||||
/* We abuse the FILE parameter to pass a GString. */
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||||
GString *s = (GString *)stream;
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||||
int initial_len = s->len;
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||||
va_list va;
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||||
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||||
va_start(va, fmt);
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||||
g_string_append_vprintf(s, fmt, va);
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||||
va_end(va);
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||||
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||||
return s->len - initial_len;
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||||
}
|
||||
|
||||
/* Look up symbol for debugging purpose. Returns "" if unknown. */
|
||||
const char *lookup_symbol(uint64_t orig_addr)
|
||||
{
|
||||
const char *symbol = "";
|
||||
struct syminfo *s;
|
||||
|
||||
for (s = syminfos; s; s = s->next) {
|
||||
symbol = s->lookup_symbol(s, orig_addr);
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||||
if (symbol[0] != '\0') {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return symbol;
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Routines for host instruction disassembly.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/disas.h"
|
||||
#include "disas/capstone.h"
|
||||
#include "disas-internal.h"
|
||||
|
||||
|
||||
/*
|
||||
* Get LENGTH bytes from info's buffer, at host address memaddr.
|
||||
* Transfer them to myaddr.
|
||||
*/
|
||||
static int host_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
|
||||
struct disassemble_info *info)
|
||||
{
|
||||
if (memaddr < info->buffer_vma
|
||||
|| memaddr + length > info->buffer_vma + info->buffer_length) {
|
||||
/* Out of bounds. Use EIO because GDB uses it. */
|
||||
return EIO;
|
||||
}
|
||||
memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Print address in hex, truncated to the width of a host virtual address. */
|
||||
static void host_print_address(bfd_vma addr, struct disassemble_info *info)
|
||||
{
|
||||
info->fprintf_func(info->stream, "0x%" PRIxPTR, (uintptr_t)addr);
|
||||
}
|
||||
|
||||
static void initialize_debug_host(CPUDebug *s)
|
||||
{
|
||||
disas_initialize_debug(s);
|
||||
|
||||
s->info.read_memory_func = host_read_memory;
|
||||
s->info.print_address_func = host_print_address;
|
||||
#if HOST_BIG_ENDIAN
|
||||
s->info.endian = BFD_ENDIAN_BIG;
|
||||
#else
|
||||
s->info.endian = BFD_ENDIAN_LITTLE;
|
||||
#endif
|
||||
#if defined(CONFIG_TCG_INTERPRETER)
|
||||
s->info.print_insn = print_insn_tci;
|
||||
#elif defined(__x86_64__)
|
||||
s->info.mach = bfd_mach_x86_64;
|
||||
s->info.cap_arch = CS_ARCH_X86;
|
||||
s->info.cap_mode = CS_MODE_64;
|
||||
s->info.cap_insn_unit = 1;
|
||||
s->info.cap_insn_split = 8;
|
||||
#elif defined(_ARCH_PPC64)
|
||||
s->info.cap_arch = CS_ARCH_PPC;
|
||||
s->info.cap_mode = CS_MODE_64;
|
||||
#elif defined(__riscv)
|
||||
#if defined(_ILP32) || (__riscv_xlen == 32)
|
||||
s->info.print_insn = print_insn_riscv32;
|
||||
#elif defined(_LP64)
|
||||
s->info.print_insn = print_insn_riscv64;
|
||||
#else
|
||||
#error unsupported RISC-V ABI
|
||||
#endif
|
||||
#elif defined(__aarch64__)
|
||||
s->info.cap_arch = CS_ARCH_ARM64;
|
||||
#elif defined(__alpha__)
|
||||
s->info.print_insn = print_insn_alpha;
|
||||
#elif defined(__sparc__)
|
||||
s->info.print_insn = print_insn_sparc;
|
||||
s->info.mach = bfd_mach_sparc_v9b;
|
||||
#elif defined(__MIPSEB__)
|
||||
s->info.print_insn = print_insn_big_mips;
|
||||
#elif defined(__MIPSEL__)
|
||||
s->info.print_insn = print_insn_little_mips;
|
||||
#elif defined(__m68k__)
|
||||
s->info.print_insn = print_insn_m68k;
|
||||
#elif defined(__s390x__)
|
||||
s->info.cap_arch = CS_ARCH_SYSTEMZ;
|
||||
s->info.cap_insn_unit = 2;
|
||||
s->info.cap_insn_split = 6;
|
||||
#elif defined(__hppa__)
|
||||
s->info.print_insn = print_insn_hppa;
|
||||
#elif defined(__loongarch__)
|
||||
s->info.print_insn = print_insn_loongarch;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Disassemble this for me please... (debugging). */
|
||||
void disas(FILE *out, const void *code, size_t size)
|
||||
{
|
||||
uintptr_t pc;
|
||||
int count;
|
||||
CPUDebug s;
|
||||
|
||||
initialize_debug_host(&s);
|
||||
s.info.fprintf_func = fprintf;
|
||||
s.info.stream = out;
|
||||
s.info.buffer = code;
|
||||
s.info.buffer_vma = (uintptr_t)code;
|
||||
s.info.buffer_length = size;
|
||||
s.info.show_opcodes = true;
|
||||
|
||||
if (s.info.cap_arch >= 0 && cap_disas_host(&s.info, code, size)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (s.info.print_insn == NULL) {
|
||||
s.info.print_insn = print_insn_od_host;
|
||||
}
|
||||
for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
|
||||
fprintf(out, "0x%08" PRIxPTR ": ", pc);
|
||||
count = s.info.print_insn(pc, &s.info);
|
||||
fprintf(out, "\n");
|
||||
if (count < 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Definitions used internally in the disassembly code
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef DISAS_INTERNAL_H
|
||||
#define DISAS_INTERNAL_H
|
||||
|
||||
#include "disas/dis-asm.h"
|
||||
|
||||
typedef struct CPUDebug {
|
||||
struct disassemble_info info;
|
||||
CPUState *cpu;
|
||||
} CPUDebug;
|
||||
|
||||
void disas_initialize_debug(CPUDebug *s);
|
||||
void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu);
|
||||
int disas_gstring_printf(FILE *stream, const char *fmt, ...)
|
||||
G_GNUC_PRINTF(2, 3);
|
||||
|
||||
int print_insn_od_host(bfd_vma pc, disassemble_info *info);
|
||||
int print_insn_od_target(bfd_vma pc, disassemble_info *info);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Functions related to disassembly from the monitor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas-internal.h"
|
||||
#include "disas/disas.h"
|
||||
#include "system/memory.h"
|
||||
#include "hw/core/cpu.h"
|
||||
#include "monitor/monitor.h"
|
||||
|
||||
/*
|
||||
* Get LENGTH bytes from info's buffer, at target address memaddr.
|
||||
* Transfer them to myaddr.
|
||||
*/
|
||||
static int
|
||||
virtual_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
|
||||
struct disassemble_info *info)
|
||||
{
|
||||
CPUDebug *s = container_of(info, CPUDebug, info);
|
||||
int r = cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
|
||||
return r ? EIO : 0;
|
||||
}
|
||||
|
||||
static int
|
||||
physical_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
|
||||
struct disassemble_info *info)
|
||||
{
|
||||
CPUDebug *s = container_of(info, CPUDebug, info);
|
||||
MemTxResult res;
|
||||
|
||||
res = address_space_read(s->cpu->as, memaddr, MEMTXATTRS_UNSPECIFIED,
|
||||
myaddr, length);
|
||||
return res == MEMTX_OK ? 0 : EIO;
|
||||
}
|
||||
|
||||
/* Disassembler for the monitor. */
|
||||
void monitor_disas(Monitor *mon, CPUState *cpu, uint64_t pc,
|
||||
int nb_insn, bool is_physical)
|
||||
{
|
||||
int count, i;
|
||||
CPUDebug s;
|
||||
g_autoptr(GString) ds = g_string_new("");
|
||||
|
||||
disas_initialize_debug_target(&s, cpu);
|
||||
s.info.fprintf_func = disas_gstring_printf;
|
||||
s.info.stream = (FILE *)ds; /* abuse this slot */
|
||||
s.info.show_opcodes = true;
|
||||
|
||||
if (is_physical) {
|
||||
s.info.read_memory_func = physical_read_memory;
|
||||
} else {
|
||||
s.info.read_memory_func = virtual_read_memory;
|
||||
}
|
||||
s.info.buffer_vma = pc;
|
||||
|
||||
if (s.info.cap_arch >= 0 && cap_disas_monitor(&s.info, pc, nb_insn)) {
|
||||
monitor_puts(mon, ds->str);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s.info.print_insn) {
|
||||
monitor_printf(mon, "0x%08" PRIx64
|
||||
": Asm output not supported on this arch\n", pc);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < nb_insn; i++) {
|
||||
g_string_append_printf(ds, "0x%08" PRIx64 ": ", pc);
|
||||
count = s.info.print_insn(pc, &s.info);
|
||||
g_string_append_c(ds, '\n');
|
||||
if (count < 0) {
|
||||
break;
|
||||
}
|
||||
pc += count;
|
||||
}
|
||||
|
||||
monitor_puts(mon, ds->str);
|
||||
}
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Routines for target instruction disassembly.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/disas.h"
|
||||
#include "disas/capstone.h"
|
||||
#include "exec/translator.h"
|
||||
#include "disas-internal.h"
|
||||
|
||||
|
||||
static int translator_read_memory(bfd_vma memaddr, bfd_byte *myaddr,
|
||||
int length, struct disassemble_info *info)
|
||||
{
|
||||
const DisasContextBase *db = info->application_data;
|
||||
return translator_st(db, myaddr, memaddr, length) ? 0 : EIO;
|
||||
}
|
||||
|
||||
void target_disas(FILE *out, CPUState *cpu, const struct DisasContextBase *db)
|
||||
{
|
||||
uint64_t code = db->pc_first;
|
||||
size_t size = translator_st_len(db);
|
||||
uint64_t pc;
|
||||
int count;
|
||||
CPUDebug s;
|
||||
|
||||
disas_initialize_debug_target(&s, cpu);
|
||||
s.info.read_memory_func = translator_read_memory;
|
||||
s.info.application_data = (void *)db;
|
||||
s.info.fprintf_func = fprintf;
|
||||
s.info.stream = out;
|
||||
s.info.buffer_vma = code;
|
||||
s.info.buffer_length = size;
|
||||
s.info.show_opcodes = true;
|
||||
|
||||
if (s.info.cap_arch >= 0 && cap_disas_target(&s.info, code, size)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (s.info.print_insn == NULL) {
|
||||
s.info.print_insn = print_insn_od_target;
|
||||
}
|
||||
|
||||
for (pc = code; size > 0; pc += count, size -= count) {
|
||||
fprintf(out, "0x%08" PRIx64 ": ", pc);
|
||||
count = s.info.print_insn(pc, &s.info);
|
||||
fprintf(out, "\n");
|
||||
if (count < 0) {
|
||||
break;
|
||||
}
|
||||
if (size < count) {
|
||||
fprintf(out,
|
||||
"Disassembler disagrees with translator over instruction "
|
||||
"decoding\n"
|
||||
"Please report this to [email protected]\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PLUGIN
|
||||
static void plugin_print_address(bfd_vma addr, struct disassemble_info *info)
|
||||
{
|
||||
/* does nothing */
|
||||
}
|
||||
|
||||
/*
|
||||
* We should only be dissembling one instruction at a time here. If
|
||||
* there is left over it usually indicates the front end has read more
|
||||
* bytes than it needed.
|
||||
*/
|
||||
char *plugin_disas(CPUState *cpu, const DisasContextBase *db,
|
||||
uint64_t addr, size_t size)
|
||||
{
|
||||
CPUDebug s;
|
||||
GString *ds = g_string_new(NULL);
|
||||
|
||||
disas_initialize_debug_target(&s, cpu);
|
||||
s.info.read_memory_func = translator_read_memory;
|
||||
s.info.application_data = (void *)db;
|
||||
s.info.fprintf_func = disas_gstring_printf;
|
||||
s.info.stream = (FILE *)ds; /* abuse this slot */
|
||||
s.info.buffer_vma = addr;
|
||||
s.info.buffer_length = size;
|
||||
s.info.print_address_func = plugin_print_address;
|
||||
|
||||
if (s.info.cap_arch >= 0 && cap_disas_plugin(&s.info, addr, size)) {
|
||||
; /* done */
|
||||
} else if (s.info.print_insn) {
|
||||
s.info.print_insn(addr, &s.info);
|
||||
} else {
|
||||
; /* cannot disassemble -- return empty string */
|
||||
}
|
||||
|
||||
/* Return the buffer, freeing the GString container. */
|
||||
return g_string_free(ds, false);
|
||||
}
|
||||
#endif /* CONFIG_PLUGIN */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* QEMU Hexagon Disassembler
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/dis-asm.h"
|
||||
#include "target/hexagon/cpu_bits.h"
|
||||
|
||||
/*
|
||||
* We will disassemble a packet with up to 4 instructions, so we need
|
||||
* a hefty size buffer.
|
||||
*/
|
||||
#define PACKET_BUFFER_LEN 1028
|
||||
|
||||
int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
uint32_t words[PACKET_WORDS_MAX];
|
||||
bool found_end = false;
|
||||
GString *buf;
|
||||
int i, len;
|
||||
|
||||
for (i = 0; i < PACKET_WORDS_MAX && !found_end; i++) {
|
||||
int status = (*info->read_memory_func)(memaddr + i * sizeof(uint32_t),
|
||||
(bfd_byte *)&words[i],
|
||||
sizeof(uint32_t), info);
|
||||
if (status) {
|
||||
if (i > 0) {
|
||||
break;
|
||||
}
|
||||
(*info->memory_error_func)(status, memaddr, info);
|
||||
return status;
|
||||
}
|
||||
if (is_packet_end(words[i])) {
|
||||
found_end = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found_end) {
|
||||
(*info->fprintf_func)(info->stream, "<invalid>");
|
||||
return PACKET_WORDS_MAX * sizeof(uint32_t);
|
||||
}
|
||||
|
||||
const HexagonCPUConfig *cfg = info->target_info;
|
||||
buf = g_string_sized_new(PACKET_BUFFER_LEN);
|
||||
len = disassemble_hexagon(words, i, memaddr, buf, cfg);
|
||||
(*info->fprintf_func)(info->stream, "%s", buf->str);
|
||||
g_string_free(buf, true);
|
||||
|
||||
return len;
|
||||
}
|
||||
+2860
File diff suppressed because it is too large
Load Diff
+5061
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,24 @@
|
||||
common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c'))
|
||||
common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
|
||||
common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
|
||||
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
|
||||
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
|
||||
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
|
||||
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
|
||||
'riscv.c',
|
||||
'riscv-xthead.c',
|
||||
'riscv-xventana.c',
|
||||
'riscv-xlrbr.c'
|
||||
))
|
||||
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
|
||||
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
|
||||
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
|
||||
common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
|
||||
common_ss.add(when: 'CONFIG_TCG', if_true: files(
|
||||
'disas-host.c',
|
||||
'disas-target.c',
|
||||
'objdump.c'
|
||||
))
|
||||
common_ss.add(files('disas-common.c'))
|
||||
system_ss.add(files('disas-mon.c'))
|
||||
specific_ss.add(capstone)
|
||||
@@ -0,0 +1,860 @@
|
||||
/* Disassemble Xilinx microblaze instructions.
|
||||
Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms are permitted
|
||||
* provided that the above copyright notice and this paragraph are
|
||||
* duplicated in all such forms and that any documentation,
|
||||
* advertising materials, and other materials related to such
|
||||
* distribution and use acknowledge that the software was developed
|
||||
* by Xilinx, Inc. The name of the Company may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Xilinx, Inc.
|
||||
*/
|
||||
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#define STATIC_TABLE
|
||||
#define DEFINE_TABLE
|
||||
|
||||
#ifndef MICROBLAZE_OPC
|
||||
#define MICROBLAZE_OPC
|
||||
/* Assembler instructions for Xilinx's microblaze processor
|
||||
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
|
||||
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms are permitted
|
||||
* provided that the above copyright notice and this paragraph are
|
||||
* duplicated in all such forms and that any documentation,
|
||||
* advertising materials, and other materials related to such
|
||||
* distribution and use acknowledge that the software was developed
|
||||
* by Xilinx, Inc. The name of the Company may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Xilinx, Inc.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef MICROBLAZE_OPCM
|
||||
#define MICROBLAZE_OPCM
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms are permitted
|
||||
* provided that the above copyright notice and this paragraph are
|
||||
* duplicated in all such forms and that any documentation,
|
||||
* advertising materials, and other materials related to such
|
||||
* distribution and use acknowledge that the software was developed
|
||||
* by Xilinx, Inc. The name of the Company may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Xilinx, Inc.
|
||||
* $Header:
|
||||
*/
|
||||
|
||||
enum microblaze_instr {
|
||||
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
|
||||
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu,
|
||||
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
|
||||
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
|
||||
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
|
||||
brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
|
||||
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
|
||||
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
|
||||
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
|
||||
bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
|
||||
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
|
||||
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt,
|
||||
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
|
||||
eget, ecget, neget, necget, eput, ecput, neput, necput,
|
||||
teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
|
||||
aget, caget, naget, ncaget, aput, caput, naput, ncaput,
|
||||
taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
|
||||
eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
|
||||
teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
|
||||
getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
|
||||
putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
|
||||
egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
|
||||
eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
|
||||
agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
|
||||
aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
|
||||
eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
|
||||
eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
|
||||
invalid_inst } ;
|
||||
|
||||
enum microblaze_instr_type {
|
||||
arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
|
||||
return_inst, immediate_inst, special_inst, memory_load_inst,
|
||||
memory_store_inst, barrel_shift_inst, anyware_inst };
|
||||
|
||||
#define INST_WORD_SIZE 4
|
||||
|
||||
/* gen purpose regs go from 0 to 31 */
|
||||
/* mask is reg num - max_reg_num, ie reg_num - 32 in this case */
|
||||
|
||||
#define REG_PC_MASK 0x8000
|
||||
#define REG_MSR_MASK 0x8001
|
||||
#define REG_EAR_MASK 0x8003
|
||||
#define REG_ESR_MASK 0x8005
|
||||
#define REG_FSR_MASK 0x8007
|
||||
#define REG_BTR_MASK 0x800b
|
||||
#define REG_EDR_MASK 0x800d
|
||||
#define REG_PVR_MASK 0xa000
|
||||
|
||||
#define REG_PID_MASK 0x9000
|
||||
#define REG_ZPR_MASK 0x9001
|
||||
#define REG_TLBX_MASK 0x9002
|
||||
#define REG_TLBLO_MASK 0x9003
|
||||
#define REG_TLBHI_MASK 0x9004
|
||||
#define REG_TLBSX_MASK 0x9005
|
||||
|
||||
#define MIN_REGNUM 0
|
||||
#define MAX_REGNUM 31
|
||||
|
||||
#define MIN_PVR_REGNUM 0
|
||||
#define MAX_PVR_REGNUM 15
|
||||
|
||||
/* 32 is REG_PC */
|
||||
#define REG_MSR 33 /* machine status reg */
|
||||
#define REG_EAR 35 /* Exception reg */
|
||||
#define REG_ESR 37 /* Exception reg */
|
||||
#define REG_FSR 39 /* FPU Status reg */
|
||||
#define REG_BTR 43 /* Branch Target reg */
|
||||
#define REG_EDR 45 /* Exception reg */
|
||||
#define REG_PVR 40960 /* Program Verification reg */
|
||||
|
||||
#define REG_PID 36864 /* MMU: Process ID reg */
|
||||
#define REG_ZPR 36865 /* MMU: Zone Protect reg */
|
||||
#define REG_TLBX 36866 /* MMU: TLB Index reg */
|
||||
#define REG_TLBLO 36867 /* MMU: TLB Low reg */
|
||||
#define REG_TLBHI 36868 /* MMU: TLB High reg */
|
||||
#define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
|
||||
|
||||
/* alternate names for gen purpose regs */
|
||||
#define REG_ROSDP 2 /* read-only small data pointer */
|
||||
#define REG_RWSDP 13 /* read-write small data pointer */
|
||||
|
||||
/* Assembler Register - Used in Delay Slot Optimization */
|
||||
#define REG_AS 18
|
||||
#define REG_ZERO 0
|
||||
|
||||
#define RD_LOW 21 /* low bit for RD */
|
||||
#define RA_LOW 16 /* low bit for RA */
|
||||
#define RB_LOW 11 /* low bit for RB */
|
||||
#define IMM_LOW 0 /* low bit for immediate */
|
||||
|
||||
#define RD_MASK 0x03E00000
|
||||
#define RA_MASK 0x001F0000
|
||||
#define RB_MASK 0x0000F800
|
||||
#define IMM_MASK 0x0000FFFF
|
||||
|
||||
// imm mask for barrel shifts
|
||||
#define IMM5_MASK 0x0000001F
|
||||
|
||||
|
||||
// FSL imm mask for get, put instructions
|
||||
#define RFSL_MASK 0x000000F
|
||||
|
||||
// imm mask for msrset, msrclr instructions
|
||||
#define IMM15_MASK 0x00007FFF
|
||||
|
||||
#endif /* MICROBLAZE-OPCM */
|
||||
|
||||
#define INST_TYPE_RD_R1_R2 0
|
||||
#define INST_TYPE_RD_R1_IMM 1
|
||||
#define INST_TYPE_RD_R1_UNSIGNED_IMM 2
|
||||
#define INST_TYPE_RD_R1 3
|
||||
#define INST_TYPE_RD_R2 4
|
||||
#define INST_TYPE_RD_IMM 5
|
||||
#define INST_TYPE_R2 6
|
||||
#define INST_TYPE_R1_R2 7
|
||||
#define INST_TYPE_R1_IMM 8
|
||||
#define INST_TYPE_IMM 9
|
||||
#define INST_TYPE_SPECIAL_R1 10
|
||||
#define INST_TYPE_RD_SPECIAL 11
|
||||
#define INST_TYPE_R1 12
|
||||
// new instn type for barrel shift imms
|
||||
#define INST_TYPE_RD_R1_IMM5 13
|
||||
#define INST_TYPE_RD_RFSL 14
|
||||
#define INST_TYPE_R1_RFSL 15
|
||||
|
||||
// new insn type for insn cache
|
||||
#define INST_TYPE_RD_R1_SPECIAL 16
|
||||
|
||||
// new insn type for msrclr, msrset insns.
|
||||
#define INST_TYPE_RD_IMM15 17
|
||||
|
||||
// new insn type for tuqula rd - addik rd, r0, 42
|
||||
#define INST_TYPE_RD 18
|
||||
|
||||
// new insn type for t*put
|
||||
#define INST_TYPE_RFSL 19
|
||||
|
||||
#define INST_TYPE_NONE 25
|
||||
|
||||
|
||||
|
||||
#define INST_PC_OFFSET 1 /* instructions where the label address is resolved as a PC offset (for branch label)*/
|
||||
#define INST_NO_OFFSET 0 /* instructions where the label address is resolved as an absolute value (for data mem or abs address)*/
|
||||
|
||||
#define IMMVAL_MASK_NON_SPECIAL 0x0000
|
||||
#define IMMVAL_MASK_MTS 0x4000
|
||||
#define IMMVAL_MASK_MFS 0x0000
|
||||
|
||||
#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only */
|
||||
#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits */
|
||||
#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16 */
|
||||
#define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */
|
||||
#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits */
|
||||
#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
|
||||
#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
|
||||
#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */
|
||||
#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */
|
||||
#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */
|
||||
#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits */
|
||||
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */
|
||||
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22 */
|
||||
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */
|
||||
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits */
|
||||
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26 */
|
||||
|
||||
// New Mask for msrset, msrclr insns.
|
||||
#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16 */
|
||||
|
||||
#define DELAY_SLOT 1
|
||||
#define NO_DELAY_SLOT 0
|
||||
|
||||
#define MAX_OPCODES 280
|
||||
|
||||
static const struct op_code_struct {
|
||||
const char *name;
|
||||
short inst_type; /* registers and immediate values involved */
|
||||
short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */
|
||||
short delay_slots; /* info about delay slots needed after this instr. */
|
||||
short immval_mask;
|
||||
unsigned long bit_sequence; /* all the fixed bits for the op are set and all the variable bits (reg names, imm vals) are set to 0 */
|
||||
unsigned long opcode_mask; /* which bits define the opcode */
|
||||
enum microblaze_instr instr;
|
||||
enum microblaze_instr_type instr_type;
|
||||
/* more info about output format here */
|
||||
} opcodes[MAX_OPCODES] =
|
||||
|
||||
{
|
||||
{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
|
||||
{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
|
||||
{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
|
||||
{"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
|
||||
{"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
|
||||
{"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
|
||||
{"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
|
||||
{"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
|
||||
{"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
|
||||
{"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
|
||||
{"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
|
||||
{"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
|
||||
{"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
|
||||
{"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
|
||||
{"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
|
||||
{"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
|
||||
{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
|
||||
{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
|
||||
{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
|
||||
{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
|
||||
{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
|
||||
{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
|
||||
{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
|
||||
{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
|
||||
{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
|
||||
{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
|
||||
{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
|
||||
{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
|
||||
{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
|
||||
{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
|
||||
{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
|
||||
{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
|
||||
{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
|
||||
{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
|
||||
{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
|
||||
{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
|
||||
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
|
||||
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
|
||||
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
|
||||
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
|
||||
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
|
||||
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
|
||||
{"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
|
||||
{"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
|
||||
{"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
|
||||
{"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
|
||||
{"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
|
||||
{"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
|
||||
{"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
|
||||
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
|
||||
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
|
||||
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
|
||||
{"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
|
||||
{"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
|
||||
{"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
|
||||
{"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
|
||||
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
|
||||
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
|
||||
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
|
||||
{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
|
||||
{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
|
||||
{"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
|
||||
{"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
|
||||
{"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
|
||||
{"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
|
||||
{"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
|
||||
{"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
|
||||
{"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
|
||||
{"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
|
||||
{"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
|
||||
{"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
|
||||
{"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
|
||||
{"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
|
||||
{"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
|
||||
{"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
|
||||
{"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
|
||||
{"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
|
||||
{"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
|
||||
{"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
|
||||
{"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
|
||||
{"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
|
||||
{"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
|
||||
{"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
|
||||
{"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
|
||||
{"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
|
||||
{"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
|
||||
{"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
|
||||
{"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
|
||||
{"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
|
||||
{"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
|
||||
{"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
|
||||
{"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
|
||||
{"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
|
||||
{"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
|
||||
{"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
|
||||
{"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
|
||||
{"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
|
||||
{"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
|
||||
{"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
|
||||
{"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
|
||||
{"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
|
||||
{"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
|
||||
{"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
|
||||
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
|
||||
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
|
||||
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
|
||||
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
|
||||
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
|
||||
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
|
||||
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
|
||||
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
|
||||
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
|
||||
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
|
||||
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
|
||||
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
|
||||
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
|
||||
{"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
|
||||
{"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
|
||||
{"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
|
||||
{"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0 */
|
||||
{"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik */
|
||||
{"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42 */
|
||||
{"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1 */
|
||||
{"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0 */
|
||||
{"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4 */
|
||||
{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */
|
||||
{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
|
||||
{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
|
||||
{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
|
||||
{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
|
||||
{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
|
||||
{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
|
||||
{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
|
||||
{"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
|
||||
{"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
|
||||
{"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
|
||||
{"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
|
||||
{"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
|
||||
{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
|
||||
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
|
||||
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
|
||||
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
|
||||
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
|
||||
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
|
||||
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
|
||||
{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
|
||||
{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
|
||||
{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
|
||||
{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
|
||||
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
|
||||
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
|
||||
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
|
||||
|
||||
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
|
||||
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
|
||||
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
|
||||
{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
|
||||
{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
|
||||
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
|
||||
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
|
||||
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
|
||||
|
||||
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
|
||||
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
|
||||
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
|
||||
{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
|
||||
{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
|
||||
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
|
||||
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
|
||||
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
|
||||
|
||||
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
|
||||
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
|
||||
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
|
||||
{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
|
||||
{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
|
||||
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
|
||||
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
|
||||
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
|
||||
|
||||
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
|
||||
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
|
||||
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
|
||||
{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
|
||||
{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
|
||||
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
|
||||
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
|
||||
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
|
||||
|
||||
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
|
||||
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
|
||||
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
|
||||
{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
|
||||
{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
|
||||
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
|
||||
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
|
||||
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
|
||||
|
||||
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
|
||||
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
|
||||
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
|
||||
{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
|
||||
{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
|
||||
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
|
||||
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
|
||||
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
|
||||
|
||||
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
|
||||
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
|
||||
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
|
||||
{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
|
||||
{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
|
||||
{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
|
||||
{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
|
||||
{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
|
||||
{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
|
||||
{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
|
||||
{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
|
||||
{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
|
||||
{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
|
||||
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
|
||||
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
|
||||
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
|
||||
|
||||
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
|
||||
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
|
||||
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
|
||||
{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
|
||||
{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
|
||||
{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
|
||||
{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
|
||||
{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
|
||||
{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
|
||||
{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
|
||||
{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
|
||||
{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
|
||||
{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
|
||||
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
|
||||
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
|
||||
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
|
||||
|
||||
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
|
||||
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
|
||||
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
|
||||
{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
|
||||
{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
|
||||
{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
|
||||
{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
|
||||
{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
|
||||
{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
|
||||
{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
|
||||
{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
|
||||
{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
|
||||
{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
|
||||
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
|
||||
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
|
||||
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
|
||||
|
||||
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
|
||||
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
|
||||
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
|
||||
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
|
||||
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
|
||||
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
|
||||
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
|
||||
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
|
||||
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
|
||||
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
|
||||
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
|
||||
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
|
||||
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
|
||||
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
|
||||
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
|
||||
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
|
||||
{"", 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
/* prefix for register names */
|
||||
#define register_prefix "r"
|
||||
|
||||
/* #defines for valid immediate range */
|
||||
#define MIN_IMM ((int) 0x80000000)
|
||||
#define MAX_IMM ((int) 0x7fffffff)
|
||||
|
||||
#define MIN_IMM15 ((int) 0x0000)
|
||||
#define MAX_IMM15 ((int) 0x7fff)
|
||||
|
||||
#endif /* MICROBLAZE_OPC */
|
||||
|
||||
#include "disas/dis-asm.h"
|
||||
|
||||
#define PRIreg register_prefix "%ld"
|
||||
#define PRIrfsl register_prefix "fsl%ld"
|
||||
#define PRIpvr register_prefix "pvr%d"
|
||||
#define PRIimm "%d"
|
||||
|
||||
#define get_field_rd(instr) ((instr & RD_MASK) >> RD_LOW)
|
||||
#define get_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
|
||||
#define get_field_r2(instr) ((instr & RB_MASK) >> RB_LOW)
|
||||
#define get_field_rfsl(instr) (instr & RFSL_MASK)
|
||||
#define get_field_imm(instr) ((int16_t)instr)
|
||||
#define get_field_imm5(instr) ((int)instr & IMM5_MASK)
|
||||
#define get_field_imm15(instr) ((int)instr & IMM15_MASK)
|
||||
|
||||
#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
|
||||
#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
|
||||
|
||||
static int get_field_special(long instr, const struct op_code_struct *op)
|
||||
{
|
||||
return ((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask;
|
||||
}
|
||||
|
||||
/* Returns NULL for PVR registers, which should be rendered differently. */
|
||||
static const char *get_special_name(int special)
|
||||
{
|
||||
switch (special) {
|
||||
case REG_MSR_MASK:
|
||||
return register_prefix "msr";
|
||||
case REG_PC_MASK:
|
||||
return register_prefix "pc";
|
||||
case REG_EAR_MASK:
|
||||
return register_prefix "ear";
|
||||
case REG_ESR_MASK:
|
||||
return register_prefix "esr";
|
||||
case REG_FSR_MASK:
|
||||
return register_prefix "fsr";
|
||||
case REG_BTR_MASK:
|
||||
return register_prefix "btr";
|
||||
case REG_EDR_MASK:
|
||||
return register_prefix "edr";
|
||||
case REG_PID_MASK:
|
||||
return register_prefix "pid";
|
||||
case REG_ZPR_MASK:
|
||||
return register_prefix "zpr";
|
||||
case REG_TLBX_MASK:
|
||||
return register_prefix "tlbx";
|
||||
case REG_TLBLO_MASK:
|
||||
return register_prefix "tlblo";
|
||||
case REG_TLBHI_MASK:
|
||||
return register_prefix "tlbhi";
|
||||
case REG_TLBSX_MASK:
|
||||
return register_prefix "tlbsx";
|
||||
default:
|
||||
if ((special & 0xE000) == REG_PVR_MASK) {
|
||||
/* pvr register */
|
||||
return NULL;
|
||||
}
|
||||
return register_prefix "pc";
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
read_insn_microblaze (bfd_vma memaddr,
|
||||
struct disassemble_info *info,
|
||||
const struct op_code_struct **opr)
|
||||
{
|
||||
unsigned char ibytes[4];
|
||||
int status;
|
||||
const struct op_code_struct *op;
|
||||
unsigned long inst;
|
||||
|
||||
status = info->read_memory_func (memaddr, ibytes, 4, info);
|
||||
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, memaddr, info);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (info->endian == BFD_ENDIAN_BIG)
|
||||
inst = ((unsigned)ibytes[0] << 24) | (ibytes[1] << 16)
|
||||
| (ibytes[2] << 8) | ibytes[3];
|
||||
else if (info->endian == BFD_ENDIAN_LITTLE)
|
||||
inst = ((unsigned)ibytes[3] << 24) | (ibytes[2] << 16)
|
||||
| (ibytes[1] << 8) | ibytes[0];
|
||||
else
|
||||
abort ();
|
||||
|
||||
/* Just a linear search of the table. */
|
||||
for (op = opcodes; op->name != 0; op ++)
|
||||
if (op->bit_sequence == (inst & op->opcode_mask))
|
||||
break;
|
||||
|
||||
*opr = op;
|
||||
return inst;
|
||||
}
|
||||
|
||||
static void print_immval_addr(struct disassemble_info *info, bool immfound,
|
||||
int immval, unsigned inst, int addend)
|
||||
{
|
||||
if (info->print_address_func && info->symbol_at_address_func) {
|
||||
if (immfound) {
|
||||
immval |= get_int_field_imm(inst) & 0x0000ffff;
|
||||
} else {
|
||||
immval = (int16_t)get_int_field_imm(inst);
|
||||
}
|
||||
immval += addend;
|
||||
if (immval != 0 && info->symbol_at_address_func(immval, info)) {
|
||||
info->fprintf_func(info->stream, "\t// ");
|
||||
info->print_address_func (immval, info);
|
||||
} else if (addend) {
|
||||
info->fprintf_func(info->stream, "\t// %x", immval);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_microblaze(bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
fprintf_function fprintf_func = info->fprintf_func;
|
||||
void *stream = info->stream;
|
||||
unsigned long inst, prev_inst;
|
||||
const struct op_code_struct *op, *pop;
|
||||
int immval = 0;
|
||||
bool immfound = false;
|
||||
static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */
|
||||
static int prev_insn_vma = -1; /*init the prev insn vma */
|
||||
int curr_insn_vma = info->buffer_vma;
|
||||
int special;
|
||||
const char *special_name;
|
||||
|
||||
info->bytes_per_chunk = 4;
|
||||
|
||||
inst = read_insn_microblaze (memaddr, info, &op);
|
||||
if (inst == 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (prev_insn_vma == curr_insn_vma) {
|
||||
if (memaddr - info->bytes_per_chunk == prev_insn_addr) {
|
||||
prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
|
||||
if (prev_inst == 0)
|
||||
return -1;
|
||||
if (pop->instr == imm) {
|
||||
immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000;
|
||||
immfound = TRUE;
|
||||
}
|
||||
else {
|
||||
immval = 0;
|
||||
immfound = FALSE;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* make curr insn as prev insn */
|
||||
prev_insn_addr = memaddr;
|
||||
prev_insn_vma = curr_insn_vma;
|
||||
|
||||
if (op->name == 0) {
|
||||
fprintf_func (stream, ".short 0x%04lx", inst);
|
||||
return 4;
|
||||
}
|
||||
|
||||
switch (op->inst_type) {
|
||||
case INST_TYPE_RD_R1_R2:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg ", " PRIreg,
|
||||
op->name, get_field_rd(inst), get_field_r1(inst),
|
||||
get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_R1_IMM:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg ", " PRIimm,
|
||||
op->name, get_field_rd(inst), get_field_r1(inst),
|
||||
get_field_imm(inst));
|
||||
if (get_int_field_r1(inst) == 0) {
|
||||
print_immval_addr(info, immfound, immval, inst, 0);
|
||||
}
|
||||
break;
|
||||
case INST_TYPE_RD_R1_IMM5:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg ", " PRIimm,
|
||||
op->name, get_field_rd(inst), get_field_r1(inst),
|
||||
get_field_imm5(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_RFSL:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIrfsl,
|
||||
op->name, get_field_rd(inst), get_field_rfsl(inst));
|
||||
break;
|
||||
case INST_TYPE_R1_RFSL:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIrfsl,
|
||||
op->name, get_field_r1(inst), get_field_rfsl(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_SPECIAL:
|
||||
special = get_field_special(inst, op);
|
||||
special_name = get_special_name(special);
|
||||
if (special_name) {
|
||||
fprintf_func(stream, "%s\t" PRIreg ", %s",
|
||||
op->name, get_field_rd(inst), special_name);
|
||||
} else {
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIpvr,
|
||||
op->name, get_field_rd(inst), special ^ REG_PVR_MASK);
|
||||
}
|
||||
break;
|
||||
case INST_TYPE_SPECIAL_R1:
|
||||
special = get_field_special(inst, op);
|
||||
special_name = get_special_name(special);
|
||||
if (special_name) {
|
||||
fprintf_func(stream, "%s\t%s, " PRIreg,
|
||||
op->name, special_name, get_field_r1(inst));
|
||||
} else {
|
||||
fprintf_func(stream, "%s\t" PRIpvr ", " PRIreg,
|
||||
op->name, special ^ REG_PVR_MASK, get_field_r1(inst));
|
||||
}
|
||||
break;
|
||||
case INST_TYPE_RD_R1:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg,
|
||||
op->name, get_field_rd(inst), get_field_r1(inst));
|
||||
break;
|
||||
case INST_TYPE_R1_R2:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg,
|
||||
op->name, get_field_r1(inst), get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_R1_IMM:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIimm,
|
||||
op->name, get_field_r1(inst), get_field_imm(inst));
|
||||
/*
|
||||
* The non-pc relative instructions are returns,
|
||||
* which shouldn't have a label printed.
|
||||
*/
|
||||
if (op->inst_offset_type == INST_PC_OFFSET) {
|
||||
print_immval_addr(info, immfound, immval, inst, memaddr);
|
||||
}
|
||||
break;
|
||||
case INST_TYPE_RD_IMM:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIimm,
|
||||
op->name, get_field_rd(inst), get_field_imm(inst));
|
||||
print_immval_addr(info, immfound, immval, inst,
|
||||
op->inst_offset_type == INST_PC_OFFSET
|
||||
? memaddr : 0);
|
||||
break;
|
||||
case INST_TYPE_IMM:
|
||||
fprintf_func(stream, "%s\t" PRIimm,
|
||||
op->name, get_field_imm(inst));
|
||||
if (op->instr != imm) {
|
||||
print_immval_addr(info, immfound, immval, inst,
|
||||
op->inst_offset_type == INST_PC_OFFSET
|
||||
? memaddr : 0);
|
||||
}
|
||||
break;
|
||||
case INST_TYPE_RD_R2:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg,
|
||||
op->name, get_field_rd(inst), get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_R2:
|
||||
fprintf_func(stream, "%s\t" PRIreg,
|
||||
op->name, get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_R1:
|
||||
fprintf_func(stream, "%s\t" PRIreg,
|
||||
op->name, get_field_r1(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_R1_SPECIAL:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIreg,
|
||||
op->name, get_field_rd(inst), get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_IMM15:
|
||||
fprintf_func(stream, "%s\t" PRIreg ", " PRIimm,
|
||||
op->name, get_field_rd(inst), get_field_imm15(inst));
|
||||
break;
|
||||
/* For tuqula instruction */
|
||||
case INST_TYPE_RD:
|
||||
fprintf_func(stream, "%s\t" PRIreg,
|
||||
op->name, get_field_rd(inst));
|
||||
break;
|
||||
case INST_TYPE_RFSL:
|
||||
fprintf_func(stream, "%s\t" PRIrfsl,
|
||||
op->name, get_field_rfsl(inst));
|
||||
break;
|
||||
default:
|
||||
/* if the disassembler lags the instruction set */
|
||||
fprintf_func(stream, "%s\tundecoded operands, inst is 0x%04lx",
|
||||
op->name, inst);
|
||||
break;
|
||||
}
|
||||
return 4;
|
||||
}
|
||||
+5818
File diff suppressed because it is too large
Load Diff
+21990
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Dump disassembly as text, for processing by scripts/disas-objdump.pl.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas-internal.h"
|
||||
|
||||
|
||||
static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
|
||||
const char *prefix)
|
||||
{
|
||||
int i, n = info->buffer_length;
|
||||
g_autofree uint8_t *buf = g_malloc(n);
|
||||
|
||||
if (info->read_memory_func(pc, buf, n, info) == 0) {
|
||||
for (i = 0; i < n; ++i) {
|
||||
if (i % 32 == 0) {
|
||||
info->fprintf_func(info->stream, "\n%s: ", prefix);
|
||||
}
|
||||
info->fprintf_func(info->stream, "%02x", buf[i]);
|
||||
}
|
||||
} else {
|
||||
info->fprintf_func(info->stream, "unable to read memory");
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
int print_insn_od_host(bfd_vma pc, disassemble_info *info)
|
||||
{
|
||||
return print_insn_objdump(pc, info, "OBJD-H");
|
||||
}
|
||||
|
||||
int print_insn_od_target(bfd_vma pc, disassemble_info *info)
|
||||
{
|
||||
return print_insn_objdump(pc, info, "OBJD-T");
|
||||
}
|
||||
@@ -0,0 +1,913 @@
|
||||
OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
|
||||
OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
|
||||
OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
|
||||
OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
|
||||
OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
|
||||
OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
|
||||
OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
|
||||
OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
|
||||
OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
|
||||
OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
|
||||
OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
|
||||
OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
|
||||
OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
|
||||
OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
|
||||
OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
|
||||
OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
|
||||
OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
|
||||
OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
|
||||
OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
|
||||
OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
|
||||
OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
|
||||
OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
|
||||
OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
|
||||
OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
|
||||
OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
|
||||
OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
|
||||
OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
|
||||
OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
|
||||
OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
|
||||
OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
|
||||
OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
|
||||
OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
|
||||
OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
|
||||
OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
|
||||
OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
|
||||
OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
|
||||
OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
|
||||
OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
|
||||
OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
|
||||
OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
|
||||
OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
|
||||
OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
|
||||
OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
|
||||
OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
|
||||
OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
|
||||
OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
|
||||
OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
|
||||
OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
|
||||
OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
|
||||
OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
|
||||
OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
|
||||
OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
|
||||
OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
|
||||
OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
|
||||
OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
|
||||
OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
|
||||
OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
|
||||
OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
|
||||
OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
|
||||
OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
|
||||
OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
|
||||
OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
|
||||
OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
|
||||
OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
|
||||
OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
|
||||
OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
|
||||
OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
|
||||
OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(dret, "dret", rv_codec_none, rv_fmt_none)
|
||||
OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
|
||||
OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
|
||||
OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
|
||||
OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
|
||||
OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
|
||||
OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
|
||||
OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
|
||||
OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
|
||||
OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d)
|
||||
OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q)
|
||||
OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s)
|
||||
OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d)
|
||||
OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q)
|
||||
OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s)
|
||||
OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d)
|
||||
OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q)
|
||||
OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s)
|
||||
OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
|
||||
OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(hret, "hret", rv_codec_none, rv_fmt_none)
|
||||
OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
|
||||
OP(j, "j", rv_codec_illegal, rv_fmt_offset)
|
||||
OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
|
||||
OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
|
||||
OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
|
||||
OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
|
||||
OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
|
||||
OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
|
||||
OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
|
||||
OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
|
||||
OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
|
||||
OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
|
||||
OP(mret, "mret", rv_codec_none, rv_fmt_none)
|
||||
OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
|
||||
OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
|
||||
OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
|
||||
OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
|
||||
OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
|
||||
OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
|
||||
OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
|
||||
OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
|
||||
OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sret, "sret", rv_codec_none, rv_fmt_none)
|
||||
OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
|
||||
OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
|
||||
OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
|
||||
OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
|
||||
OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
|
||||
OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(uret, "uret", rv_codec_none, rv_fmt_none)
|
||||
OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
|
||||
OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
|
||||
OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
|
||||
OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
|
||||
OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
|
||||
OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
|
||||
OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
|
||||
OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vloxei16_v, "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei32_v, "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei64_v, "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vluxei16_v, "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei32_v, "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei64_v, "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
|
||||
OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
|
||||
OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
|
||||
OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
|
||||
OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
|
||||
OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
|
||||
OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
|
||||
OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
|
||||
OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
|
||||
OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
|
||||
OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
|
||||
OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
|
||||
@@ -0,0 +1,8 @@
|
||||
OP(crc32_b, "crc32.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_h, "crc32.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_w, "crc32.w", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_d, "crc32.d", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_b, "crc32c.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_h, "crc32c.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_w, "crc32c.w", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_d, "crc32c.d", rv_codec_r, rv_fmt_rd_rs1)
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
|
||||
* bitmanip extension v0.93.
|
||||
*
|
||||
* Copyright (c) 2023 Rivos Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xlrbr.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xlrbr-op.c.inc"
|
||||
#undef OP
|
||||
|
||||
const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch ((inst >> 0) & 0b1111111) {
|
||||
case 0b0010011:
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 0b001:
|
||||
switch ((inst >> 20 & 0b111111111111)) {
|
||||
case 0b011000010000:
|
||||
return &op_crc32_b;
|
||||
case 0b011000010001:
|
||||
return &op_crc32_h;
|
||||
case 0b011000010010:
|
||||
return &op_crc32_w;
|
||||
case 0b011000010011:
|
||||
return &op_crc32_d;
|
||||
case 0b011000011000:
|
||||
return &op_crc32c_b;
|
||||
case 0b011000011001:
|
||||
return &op_crc32c_h;
|
||||
case 0b011000011010:
|
||||
return &op_crc32c_w;
|
||||
case 0b011000011011:
|
||||
return &op_crc32c_d;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
|
||||
* bitmanip extension v0.93.
|
||||
*
|
||||
* Copyright (c) 2023 Rivos Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef DISAS_RISCV_XLRBR_H
|
||||
#define DISAS_RISCV_XLRBR_H
|
||||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xlrbr(rv_decode *, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XLRBR_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/* XTheadBa */
|
||||
OP(th_addsl, "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadBb */
|
||||
OP(th_srri, "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
|
||||
OP(th_srriw, "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm)
|
||||
OP(th_ext, "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
|
||||
OP(th_extu, "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
|
||||
OP(th_ff0, "th.ff0", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_ff1, "th.ff1", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_rev, "th.rev", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_revw, "th.revw", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_tstnbz, "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
|
||||
/* XTheadBs */
|
||||
OP(th_tst, "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
|
||||
|
||||
/* XTheadCmo */
|
||||
OP(th_dcache_call, "th.dcache.call", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_ciall, "th.dcache.ciall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_iall, "th.dcache.iall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_cpa, "th.dcache.cpa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cipa, "th.dcache.cipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_ipa, "th.dcache.ipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cva, "th.dcache.cva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_civa, "th.dcache.civa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_iva, "th.dcache.iva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_csw, "th.dcache.csw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cisw, "th.dcache.cisw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_isw, "th.dcache.isw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cpal1, "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cval1, "th.dcache.cval1", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_icache_iall, "th.icache.iall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_icache_ialls, "th.icache.ialls", rv_codec_none, rv_fmt_none)
|
||||
OP(th_icache_ipa, "th.icache.ipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_icache_iva, "th.icache.iva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_l2cache_call, "th.l2cache.call", rv_codec_none, rv_fmt_none)
|
||||
OP(th_l2cache_ciall, "th.l2cache.ciall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_l2cache_iall, "th.l2cache.iall", rv_codec_none, rv_fmt_none)
|
||||
|
||||
/* XTheadCondMov */
|
||||
OP(th_mveqz, "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mvnez, "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
|
||||
/* XTheadFMemIdx */
|
||||
OP(th_flrd, "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flrw, "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flurd, "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flurw, "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsrd, "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsrw, "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsurd, "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsurw, "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadFmv */
|
||||
OP(th_fmv_hw_x, "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(th_fmv_x_hw, "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1)
|
||||
|
||||
/* XTheadMac */
|
||||
OP(th_mula, "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulaw, "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulah, "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_muls, "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulsw, "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulsh, "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
|
||||
/* XTheadMemIdx */
|
||||
OP(th_lbia, "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbib, "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbuia, "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbuib, "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhia, "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhib, "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhuia, "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhuib, "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwia, "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwib, "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwuia, "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwuib, "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_ldia, "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_ldib, "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sbia, "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sbib, "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_shia, "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_shib, "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_swia, "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_swib, "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sdia, "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sdib, "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lrb, "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrbu, "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrh, "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrhu, "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrw, "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrwu, "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrd, "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srb, "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srh, "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srw, "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srd, "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurb, "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurbu, "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurh, "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurhu, "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurw, "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurwu, "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurd, "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surb, "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surh, "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surw, "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surd, "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadMemPair */
|
||||
OP(th_ldd, "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_lwd, "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_lwud, "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_sdd, "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_swd, "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
|
||||
/* XTheadSync */
|
||||
OP(th_sfence_vmas, "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2)
|
||||
OP(th_sync, "th.sync", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_i, "th.sync.i", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_is, "th.sync.is", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_s, "th.sync.s", rv_codec_none, rv_fmt_none)
|
||||
@@ -0,0 +1,465 @@
|
||||
/*
|
||||
* QEMU RISC-V Disassembler for xthead.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xthead.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xthead-op.c.inc"
|
||||
#undef OP
|
||||
|
||||
const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0000000:
|
||||
case 0b0000001:
|
||||
case 0b0000010:
|
||||
case 0b0000011: return &op_th_addsl;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0001010: return &op_th_srriw;
|
||||
case 0b1000000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_tstnbz;
|
||||
}
|
||||
break;
|
||||
case 0b1000001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_rev;
|
||||
}
|
||||
break;
|
||||
case 0b1000010:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_ff0;
|
||||
}
|
||||
break;
|
||||
case 0b1000011:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_ff1;
|
||||
}
|
||||
break;
|
||||
case 0b1000100:
|
||||
case 0b1001000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_revw;
|
||||
}
|
||||
break;
|
||||
case 0b0001000:
|
||||
case 0b0001001:
|
||||
return &op_th_srri;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: return &op_th_ext;
|
||||
case 3: return &op_th_extu;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 26) & 0b111111) {
|
||||
case 0b100010: return &op_th_tst;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 0:
|
||||
switch ((inst >> 20 & 0b111111111111)) {
|
||||
case 0b000000000001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_call;
|
||||
}
|
||||
break;
|
||||
case 0b000000000011:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_ciall;
|
||||
}
|
||||
break;
|
||||
case 0b000000000010:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_iall;
|
||||
}
|
||||
break;
|
||||
case 0b000000101001: return &op_th_dcache_cpa;
|
||||
case 0b000000101011: return &op_th_dcache_cipa;
|
||||
case 0b000000101010: return &op_th_dcache_ipa;
|
||||
case 0b000000100101: return &op_th_dcache_cva;
|
||||
case 0b000000100111: return &op_th_dcache_civa;
|
||||
case 0b000000100110: return &op_th_dcache_iva;
|
||||
case 0b000000100001: return &op_th_dcache_csw;
|
||||
case 0b000000100011: return &op_th_dcache_cisw;
|
||||
case 0b000000100010: return &op_th_dcache_isw;
|
||||
case 0b000000101000: return &op_th_dcache_cpal1;
|
||||
case 0b000000100100: return &op_th_dcache_cval1;
|
||||
case 0b000000010000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_icache_iall;
|
||||
}
|
||||
break;
|
||||
case 0b000000010001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_icache_ialls;
|
||||
}
|
||||
break;
|
||||
case 0b000000111000: return &op_th_icache_ipa;
|
||||
case 0b000000110000: return &op_th_icache_iva;
|
||||
case 0b000000010101:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_call;
|
||||
}
|
||||
break;
|
||||
case 0b000000010111:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_ciall;
|
||||
}
|
||||
break;
|
||||
case 0b000000010110:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_iall;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0100000: return &op_th_mveqz;
|
||||
case 0b0100001: return &op_th_mvnez;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 6:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 8: return &op_th_flrw;
|
||||
case 10: return &op_th_flurw;
|
||||
case 12: return &op_th_flrd;
|
||||
case 14: return &op_th_flurd;
|
||||
}
|
||||
break;
|
||||
case 7:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 8: return &op_th_fsrw;
|
||||
case 10: return &op_th_fsurw;
|
||||
case 12: return &op_th_fsrd;
|
||||
case 14: return &op_th_fsurd;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b1010000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_fmv_hw_x;
|
||||
}
|
||||
break;
|
||||
case 0b1100000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_fmv_x_hw;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0010000: return &op_th_mula;
|
||||
case 0b0010001: return &op_th_muls;
|
||||
case 0b0010010: return &op_th_mulaw;
|
||||
case 0b0010011: return &op_th_mulsw;
|
||||
case 0b0010100: return &op_th_mulah;
|
||||
case 0b0010101: return &op_th_mulsh;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 4:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 0: return &op_th_lrb;
|
||||
case 1: return &op_th_lbib;
|
||||
case 2: return &op_th_lurb;
|
||||
case 3: return &op_th_lbia;
|
||||
case 4: return &op_th_lrh;
|
||||
case 5: return &op_th_lhib;
|
||||
case 6: return &op_th_lurh;
|
||||
case 7: return &op_th_lhia;
|
||||
case 8: return &op_th_lrw;
|
||||
case 9: return &op_th_lwib;
|
||||
case 10: return &op_th_lurw;
|
||||
case 11: return &op_th_lwia;
|
||||
case 12: return &op_th_lrd;
|
||||
case 13: return &op_th_ldib;
|
||||
case 14: return &op_th_lurd;
|
||||
case 15: return &op_th_ldia;
|
||||
case 16: return &op_th_lrbu;
|
||||
case 17: return &op_th_lbuib;
|
||||
case 18: return &op_th_lurbu;
|
||||
case 19: return &op_th_lbuia;
|
||||
case 20: return &op_th_lrhu;
|
||||
case 21: return &op_th_lhuib;
|
||||
case 22: return &op_th_lurhu;
|
||||
case 23: return &op_th_lhuia;
|
||||
case 24: return &op_th_lrwu;
|
||||
case 25: return &op_th_lwuib;
|
||||
case 26: return &op_th_lurwu;
|
||||
case 27: return &op_th_lwuia;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 0: return &op_th_srb;
|
||||
case 1: return &op_th_sbib;
|
||||
case 2: return &op_th_surb;
|
||||
case 3: return &op_th_sbia;
|
||||
case 4: return &op_th_srh;
|
||||
case 5: return &op_th_shib;
|
||||
case 6: return &op_th_surh;
|
||||
case 7: return &op_th_shia;
|
||||
case 8: return &op_th_srw;
|
||||
case 9: return &op_th_swib;
|
||||
case 10: return &op_th_surw;
|
||||
case 11: return &op_th_swia;
|
||||
case 12: return &op_th_srd;
|
||||
case 13: return &op_th_sdib;
|
||||
case 14: return &op_th_surd;
|
||||
case 15: return &op_th_sdia;
|
||||
}
|
||||
break;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 4:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 28: return &op_th_lwd;
|
||||
case 30: return &op_th_lwud;
|
||||
case 31: return &op_th_ldd;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 28: return &op_th_swd;
|
||||
case 31: return &op_th_sdd;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 2:
|
||||
/* custom-0 */
|
||||
switch ((inst >> 12) & 0b111) {
|
||||
case 0:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0000010: return &op_th_sfence_vmas;
|
||||
case 0b0000000:
|
||||
switch ((inst >> 20) & 0b11111) {
|
||||
case 0b11000: return &op_th_sync;
|
||||
case 0b11010: return &op_th_sync_i;
|
||||
case 0b11011: return &op_th_sync_is;
|
||||
case 0b11001: return &op_th_sync_s;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* QEMU disassembler -- RISC-V specific header (xthead*).
|
||||
*
|
||||
* Copyright (c) 2023 VRULL GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef DISAS_RISCV_XTHEAD_H
|
||||
#define DISAS_RISCV_XTHEAD_H
|
||||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xtheadba(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadbb(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadbs(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadcmo(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadcondmov(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadfmv(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmac(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmemidx(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmempair(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadsync(rv_decode *, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XTHEAD_H */
|
||||
@@ -0,0 +1,2 @@
|
||||
OP(vt_maskc, "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(vt_maskcn, "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* QEMU RISC-V Disassembler for xventana.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xventana.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xventana-op.c.inc"
|
||||
#undef OP
|
||||
|
||||
const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 30:
|
||||
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
|
||||
case 6: return &op_vt_maskc;
|
||||
case 7: return &op_vt_maskcn;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* QEMU disassembler -- RISC-V specific header (xventana*).
|
||||
*
|
||||
* Copyright (c) 2023 VRULL GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef DISAS_RISCV_XVENTANA_H
|
||||
#define DISAS_RISCV_XVENTANA_H
|
||||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xventanacondops(rv_decode*, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XVENTANA_H */
|
||||
+3543
File diff suppressed because it is too large
Load Diff
+294
@@ -0,0 +1,294 @@
|
||||
/*
|
||||
* QEMU disassembler -- RISC-V specific header.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef DISAS_RISCV_H
|
||||
#define DISAS_RISCV_H
|
||||
|
||||
#include "target/riscv/cpu_cfg.h"
|
||||
|
||||
/* types */
|
||||
|
||||
typedef uint32_t rv_inst;
|
||||
typedef uint16_t rv_opcode;
|
||||
|
||||
/* enums */
|
||||
|
||||
typedef enum {
|
||||
rv32,
|
||||
rv64,
|
||||
rv128
|
||||
} rv_isa;
|
||||
|
||||
typedef enum {
|
||||
rv_rm_rne = 0,
|
||||
rv_rm_rtz = 1,
|
||||
rv_rm_rdn = 2,
|
||||
rv_rm_rup = 3,
|
||||
rv_rm_rmm = 4,
|
||||
rv_rm_dyn = 7,
|
||||
} rv_rm;
|
||||
|
||||
typedef enum {
|
||||
rv_fence_i = 8,
|
||||
rv_fence_o = 4,
|
||||
rv_fence_r = 2,
|
||||
rv_fence_w = 1,
|
||||
} rv_fence;
|
||||
|
||||
typedef enum {
|
||||
rv_ireg_zero,
|
||||
rv_ireg_ra,
|
||||
rv_ireg_sp,
|
||||
rv_ireg_gp,
|
||||
rv_ireg_tp,
|
||||
rv_ireg_t0,
|
||||
rv_ireg_t1,
|
||||
rv_ireg_t2,
|
||||
rv_ireg_s0,
|
||||
rv_ireg_s1,
|
||||
rv_ireg_a0,
|
||||
rv_ireg_a1,
|
||||
rv_ireg_a2,
|
||||
rv_ireg_a3,
|
||||
rv_ireg_a4,
|
||||
rv_ireg_a5,
|
||||
rv_ireg_a6,
|
||||
rv_ireg_a7,
|
||||
rv_ireg_s2,
|
||||
rv_ireg_s3,
|
||||
rv_ireg_s4,
|
||||
rv_ireg_s5,
|
||||
rv_ireg_s6,
|
||||
rv_ireg_s7,
|
||||
rv_ireg_s8,
|
||||
rv_ireg_s9,
|
||||
rv_ireg_s10,
|
||||
rv_ireg_s11,
|
||||
rv_ireg_t3,
|
||||
rv_ireg_t4,
|
||||
rv_ireg_t5,
|
||||
rv_ireg_t6,
|
||||
} rv_ireg;
|
||||
|
||||
typedef enum {
|
||||
rvc_end,
|
||||
rvc_rd_eq_ra,
|
||||
rvc_rd_eq_x0,
|
||||
rvc_rs1_eq_x0,
|
||||
rvc_rs2_eq_x0,
|
||||
rvc_rs2_eq_rs1,
|
||||
rvc_rs1_eq_ra,
|
||||
rvc_imm_eq_zero,
|
||||
rvc_imm_eq_n1,
|
||||
rvc_imm_eq_p1,
|
||||
} rvc_constraint;
|
||||
|
||||
typedef enum {
|
||||
rv_codec_illegal,
|
||||
rv_codec_none,
|
||||
rv_codec_u,
|
||||
rv_codec_uj,
|
||||
rv_codec_i,
|
||||
rv_codec_i_sh5,
|
||||
rv_codec_i_sh6,
|
||||
rv_codec_i_sh7,
|
||||
rv_codec_i_csr,
|
||||
rv_codec_s,
|
||||
rv_codec_sb,
|
||||
rv_codec_r,
|
||||
rv_codec_r_m,
|
||||
rv_codec_r4_m,
|
||||
rv_codec_r_a,
|
||||
rv_codec_r_l,
|
||||
rv_codec_r_f,
|
||||
rv_codec_cb,
|
||||
rv_codec_cb_imm,
|
||||
rv_codec_cb_sh5,
|
||||
rv_codec_cb_sh6,
|
||||
rv_codec_ci,
|
||||
rv_codec_ci_sh5,
|
||||
rv_codec_ci_sh6,
|
||||
rv_codec_ci_16sp,
|
||||
rv_codec_ci_lwsp,
|
||||
rv_codec_ci_ldsp,
|
||||
rv_codec_ci_lqsp,
|
||||
rv_codec_ci_li,
|
||||
rv_codec_ci_lui,
|
||||
rv_codec_ci_none,
|
||||
rv_codec_ciw_4spn,
|
||||
rv_codec_cj,
|
||||
rv_codec_cj_jal,
|
||||
rv_codec_cl_lw,
|
||||
rv_codec_cl_ld,
|
||||
rv_codec_cl_lq,
|
||||
rv_codec_cr,
|
||||
rv_codec_cr_mv,
|
||||
rv_codec_cr_jalr,
|
||||
rv_codec_cr_jr,
|
||||
rv_codec_cs,
|
||||
rv_codec_cs_sw,
|
||||
rv_codec_cs_sd,
|
||||
rv_codec_cs_sq,
|
||||
rv_codec_css_swsp,
|
||||
rv_codec_css_sdsp,
|
||||
rv_codec_css_sqsp,
|
||||
rv_codec_k_bs,
|
||||
rv_codec_k_rnum,
|
||||
rv_codec_v_r,
|
||||
rv_codec_v_ldst,
|
||||
rv_codec_v_i,
|
||||
rv_codec_v_i_u,
|
||||
rv_codec_vsetvli,
|
||||
rv_codec_vsetivli,
|
||||
rv_codec_vror_vi,
|
||||
rv_codec_zcb_ext,
|
||||
rv_codec_zcb_mul,
|
||||
rv_codec_zcb_lb,
|
||||
rv_codec_zcb_lh,
|
||||
rv_codec_zcmp_cm_pushpop,
|
||||
rv_codec_zcmp_cm_mv,
|
||||
rv_codec_zcmt_jt,
|
||||
rv_codec_r2_imm5,
|
||||
rv_codec_r2,
|
||||
rv_codec_r2_imm6,
|
||||
rv_codec_r_imm2,
|
||||
rv_codec_r2_immhl,
|
||||
rv_codec_r2_imm2_imm5,
|
||||
rv_codec_fli,
|
||||
rv_codec_lp,
|
||||
rv_codec_cmop,
|
||||
rv_codec_cmop_ss,
|
||||
rv_codec_mop_r,
|
||||
rv_codec_mop_rr,
|
||||
} rv_codec;
|
||||
|
||||
/* structures */
|
||||
|
||||
typedef struct rv_opcode_data rv_opcode_data;
|
||||
|
||||
typedef struct {
|
||||
const rv_opcode_data *op;
|
||||
const rvc_constraint *constraints;
|
||||
} rv_comp_data;
|
||||
|
||||
struct rv_opcode_data {
|
||||
const char *name;
|
||||
rv_codec codec;
|
||||
const char *format;
|
||||
const rv_comp_data *pseudo;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
const RISCVCPUConfig *cfg;
|
||||
uint64_t pc;
|
||||
uint64_t inst;
|
||||
int32_t imm;
|
||||
int32_t imm1;
|
||||
uint8_t rd;
|
||||
uint8_t rs1;
|
||||
uint8_t rs2;
|
||||
uint8_t rs3;
|
||||
uint8_t rm;
|
||||
uint8_t pred;
|
||||
uint8_t succ;
|
||||
uint8_t aq;
|
||||
uint8_t rl;
|
||||
uint8_t bs;
|
||||
uint8_t rnum;
|
||||
uint8_t vm;
|
||||
uint32_t vzimm;
|
||||
uint8_t rlist;
|
||||
} rv_decode;
|
||||
|
||||
/* instruction formats */
|
||||
|
||||
#define rv_fmt_none "O\t"
|
||||
#define rv_fmt_rs1 "O\t1"
|
||||
#define rv_fmt_rs2 "O\t2"
|
||||
#define rv_fmt_offset "O\to"
|
||||
#define rv_fmt_pred_succ "O\tp,s"
|
||||
#define rv_fmt_rs1_rs2 "O\t1,2"
|
||||
#define rv_fmt_rd_imm "O\t0,i"
|
||||
#define rv_fmt_rd_uimm "O\t0,Ui"
|
||||
#define rv_fmt_imm "O\ti"
|
||||
#define rv_fmt_rd_offset "O\t0,o"
|
||||
#define rv_fmt_rd_uoffset "O\t0,Uo"
|
||||
#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
|
||||
#define rv_fmt_frd_rs1 "O\t3,1"
|
||||
#define rv_fmt_frd_rs1_rs2 "O\t3,1,2"
|
||||
#define rv_fmt_frd_frs1 "O\t3,4"
|
||||
#define rv_fmt_rd_frs1 "O\t0,4"
|
||||
#define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
|
||||
#define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
|
||||
#define rv_fmt_rm_frd_frs1 "O\tr,3,4"
|
||||
#define rv_fmt_rm_frd_rs1 "O\tr,3,1"
|
||||
#define rv_fmt_rm_rd_frs1 "O\tr,0,4"
|
||||
#define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5"
|
||||
#define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6"
|
||||
#define rv_fmt_rd_rs1_imm "O\t0,1,i"
|
||||
#define rv_fmt_rd_rs1_offset "O\t0,1,i"
|
||||
#define rv_fmt_rd_offset_rs1 "O\t0,i(1)"
|
||||
#define rv_fmt_frd_offset_rs1 "O\t3,i(1)"
|
||||
#define rv_fmt_rd_csr_rs1 "O\t0,c,1"
|
||||
#define rv_fmt_rd_csr_zimm "O\t0,c,7"
|
||||
#define rv_fmt_rs2_offset_rs1 "O\t2,i(1)"
|
||||
#define rv_fmt_frs2_offset_rs1 "O\t5,i(1)"
|
||||
#define rv_fmt_rs1_rs2_offset "O\t1,2,o"
|
||||
#define rv_fmt_rs2_rs1_offset "O\t2,1,o"
|
||||
#define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)"
|
||||
#define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)"
|
||||
#define rv_fmt_rd "O\t0"
|
||||
#define rv_fmt_rd_zimm "O\t0,7"
|
||||
#define rv_fmt_rd_rs1 "O\t0,1"
|
||||
#define rv_fmt_rd_rs2 "O\t0,2"
|
||||
#define rv_fmt_rs1_offset "O\t1,o"
|
||||
#define rv_fmt_rs2_offset "O\t2,o"
|
||||
#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
|
||||
#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
|
||||
#define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m"
|
||||
#define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m"
|
||||
#define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm"
|
||||
#define rv_fmt_vd_vs2_vs1 "O\tD,F,E"
|
||||
#define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El"
|
||||
#define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em"
|
||||
#define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l"
|
||||
#define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l"
|
||||
#define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m"
|
||||
#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
|
||||
#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
|
||||
#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
|
||||
#define rv_fmt_vd_vs2_uimm "O\tD,F,u"
|
||||
#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
|
||||
#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
|
||||
#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
|
||||
#define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm"
|
||||
#define rv_fmt_vd_vs1 "O\tD,E"
|
||||
#define rv_fmt_vd_rs1 "O\tD,1"
|
||||
#define rv_fmt_vd_fs1 "O\tD,4"
|
||||
#define rv_fmt_vd_imm "O\tD,i"
|
||||
#define rv_fmt_vd_vs2 "O\tD,F"
|
||||
#define rv_fmt_vd_vs2_vm "O\tD,Fm"
|
||||
#define rv_fmt_rd_vs2_vm "O\t0,Fm"
|
||||
#define rv_fmt_rd_vs2 "O\t0,F"
|
||||
#define rv_fmt_fd_vs2 "O\t3,F"
|
||||
#define rv_fmt_vd_vm "O\tDm"
|
||||
#define rv_fmt_vsetvli "O\t0,1,v"
|
||||
#define rv_fmt_vsetivli "O\t0,i,v"
|
||||
#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
|
||||
#define rv_fmt_push_rlist "O\tx,-i"
|
||||
#define rv_fmt_pop_rlist "O\tx,i"
|
||||
#define rv_fmt_zcmt_index "O\ti"
|
||||
#define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i"
|
||||
#define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i"
|
||||
#define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j"
|
||||
#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
|
||||
#define rv_fmt_rd2_imm "O\t0,2,(1),i"
|
||||
#define rv_fmt_fli "O\t3,h"
|
||||
#define rv_fmt_cmop "O.i"
|
||||
#define rv_fmt_mop_r "O.i\t0,1"
|
||||
#define rv_fmt_mop_rr "O.i\t0,1,2"
|
||||
|
||||
#endif /* DISAS_RISCV_H */
|
||||
+2073
File diff suppressed because it is too large
Load Diff
+3236
File diff suppressed because it is too large
Load Diff
+133
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/dis-asm.h"
|
||||
#include "hw/xtensa/xtensa-isa.h"
|
||||
|
||||
int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
xtensa_isa isa = info->private_data;
|
||||
xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc(isa);
|
||||
xtensa_insnbuf slotbuf = xtensa_insnbuf_alloc(isa);
|
||||
bfd_byte *buffer = g_malloc(1);
|
||||
int status = info->read_memory_func(memaddr, buffer, 1, info);
|
||||
xtensa_format fmt;
|
||||
int slot, slots;
|
||||
unsigned len;
|
||||
|
||||
if (status) {
|
||||
info->memory_error_func(status, memaddr, info);
|
||||
len = -1;
|
||||
goto out;
|
||||
}
|
||||
len = xtensa_isa_length_from_chars(isa, buffer);
|
||||
if (len == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
|
||||
len = 1;
|
||||
goto out;
|
||||
}
|
||||
buffer = g_realloc(buffer, len);
|
||||
status = info->read_memory_func(memaddr + 1, buffer + 1, len - 1, info);
|
||||
if (status) {
|
||||
info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
|
||||
info->memory_error_func(status, memaddr + 1, info);
|
||||
len = 1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
xtensa_insnbuf_from_chars(isa, insnbuf, buffer, len);
|
||||
fmt = xtensa_format_decode(isa, insnbuf);
|
||||
if (fmt == XTENSA_UNDEFINED) {
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < len; ++i) {
|
||||
info->fprintf_func(info->stream, "%s 0x%02x",
|
||||
i ? ", " : ".byte ", buffer[i]);
|
||||
}
|
||||
goto out;
|
||||
}
|
||||
slots = xtensa_format_num_slots(isa, fmt);
|
||||
|
||||
if (slots > 1) {
|
||||
info->fprintf_func(info->stream, "{ ");
|
||||
}
|
||||
|
||||
for (slot = 0; slot < slots; ++slot) {
|
||||
xtensa_opcode opc;
|
||||
int opnd, vopnd, opnds;
|
||||
|
||||
if (slot) {
|
||||
info->fprintf_func(info->stream, "; ");
|
||||
}
|
||||
xtensa_format_get_slot(isa, fmt, slot, insnbuf, slotbuf);
|
||||
opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf);
|
||||
if (opc == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, "???");
|
||||
continue;
|
||||
}
|
||||
opnds = xtensa_opcode_num_operands(isa, opc);
|
||||
|
||||
info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc));
|
||||
|
||||
for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
|
||||
if (xtensa_operand_is_visible(isa, opc, opnd)) {
|
||||
uint32_t v = 0xbadc0de;
|
||||
int rc;
|
||||
|
||||
info->fprintf_func(info->stream, vopnd ? ", " : "\t");
|
||||
xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
|
||||
slotbuf, &v);
|
||||
rc = xtensa_operand_decode(isa, opc, opnd, &v);
|
||||
if (rc == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, "???");
|
||||
} else if (xtensa_operand_is_register(isa, opc, opnd)) {
|
||||
xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
|
||||
|
||||
info->fprintf_func(info->stream, "%s%d",
|
||||
xtensa_regfile_shortname(isa, rf), v);
|
||||
} else if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
|
||||
xtensa_operand_undo_reloc(isa, opc, opnd, &v, memaddr);
|
||||
info->fprintf_func(info->stream, "0x%x", v);
|
||||
} else {
|
||||
info->fprintf_func(info->stream, "%d", v);
|
||||
}
|
||||
++vopnd;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (slots > 1) {
|
||||
info->fprintf_func(info->stream, " }");
|
||||
}
|
||||
|
||||
out:
|
||||
g_free(buffer);
|
||||
xtensa_insnbuf_free(isa, insnbuf);
|
||||
xtensa_insnbuf_free(isa, slotbuf);
|
||||
|
||||
return len;
|
||||
}
|
||||
Reference in New Issue
Block a user