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Import QEMU upstream snapshot d2e570c

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Upstream: https://gitlab.com/qemu-project/qemu.git

Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
This commit is contained in:
Yaya48
2026-08-31 02:15:30 +02:00
commit cf256aa081
11315 changed files with 3598369 additions and 0 deletions
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hw/adc/Kconfig
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config STM32F2XX_ADC
bool
hw/adc/aspeed_adc.c
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/*
* Aspeed ADC
*
* Copyright 2017-2021 IBM Corp.
*
* Andrew Jeffery <[email protected]>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "hw/core/irq.h"
#include "hw/core/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/adc/aspeed_adc.h"
#include "trace.h"
#define ASPEED_ADC_MEMORY_REGION_SIZE 0x1000
#define ASPEED_ADC_ENGINE_MEMORY_REGION_SIZE 0x100
#define ASPEED_ADC_ENGINE_CH_EN_MASK 0xffff0000
#define ASPEED_ADC_ENGINE_CH_EN(x) ((BIT(x)) << 16)
#define ASPEED_ADC_ENGINE_INIT BIT(8)
#define ASPEED_ADC_ENGINE_AUTO_COMP BIT(5)
#define ASPEED_ADC_ENGINE_COMP BIT(4)
#define ASPEED_ADC_ENGINE_MODE_MASK 0x0000000e
#define ASPEED_ADC_ENGINE_MODE_OFF (0b000 << 1)
#define ASPEED_ADC_ENGINE_MODE_STANDBY (0b001 << 1)
#define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1)
#define ASPEED_ADC_ENGINE_EN BIT(0)
#define ASPEED_ADC_HYST_EN BIT(31)
#define ASPEED_ADC_L_MASK ((1 << 10) - 1)
#define ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK)
#define ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK)
#define ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 | ASPEED_ADC_L_MASK)
#define LOWER_CHANNEL_MASK ((1 << 10) - 1)
#define LOWER_CHANNEL_DATA(x) ((x) & LOWER_CHANNEL_MASK)
#define UPPER_CHANNEL_DATA(x) (((x) >> 16) & LOWER_CHANNEL_MASK)
#define TO_REG(addr) (addr >> 2)
#define ENGINE_CONTROL TO_REG(0x00)
#define INTERRUPT_CONTROL TO_REG(0x04)
#define VGA_DETECT_CONTROL TO_REG(0x08)
#define CLOCK_CONTROL TO_REG(0x0C)
#define DATA_CHANNEL_1_AND_0 TO_REG(0x10)
#define DATA_CHANNEL_7_AND_6 TO_REG(0x1C)
#define DATA_CHANNEL_9_AND_8 TO_REG(0x20)
#define DATA_CHANNEL_15_AND_14 TO_REG(0x2C)
#define BOUNDS_CHANNEL_0 TO_REG(0x30)
#define BOUNDS_CHANNEL_7 TO_REG(0x4C)
#define BOUNDS_CHANNEL_8 TO_REG(0x50)
#define BOUNDS_CHANNEL_15 TO_REG(0x6C)
#define HYSTERESIS_CHANNEL_0 TO_REG(0x70)
#define HYSTERESIS_CHANNEL_7 TO_REG(0x8C)
#define HYSTERESIS_CHANNEL_8 TO_REG(0x90)
#define HYSTERESIS_CHANNEL_15 TO_REG(0xAC)
#define INTERRUPT_SOURCE TO_REG(0xC0)
#define COMPENSATING_AND_TRIMMING TO_REG(0xC4)
static inline uint32_t update_channels(uint32_t current)
{
return ((((current >> 16) & ASPEED_ADC_L_MASK) + 7) << 16) |
((current + 5) & ASPEED_ADC_L_MASK);
}
static bool breaks_threshold(AspeedADCEngineState *s, int reg)
{
assert(reg >= DATA_CHANNEL_1_AND_0 &&
reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2);
int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2;
int b_bounds_reg = a_bounds_reg + 1;
uint32_t a_and_b = s->regs[reg];
uint32_t a_bounds = s->regs[a_bounds_reg];
uint32_t b_bounds = s->regs[b_bounds_reg];
uint32_t a = ASPEED_ADC_L(a_and_b);
uint32_t b = ASPEED_ADC_H(a_and_b);
uint32_t a_lower = ASPEED_ADC_L(a_bounds);
uint32_t a_upper = ASPEED_ADC_H(a_bounds);
uint32_t b_lower = ASPEED_ADC_L(b_bounds);
uint32_t b_upper = ASPEED_ADC_H(b_bounds);
return (a < a_lower || a > a_upper) ||
(b < b_lower || b > b_upper);
}
static uint32_t read_channel_sample(AspeedADCEngineState *s, int reg)
{
assert(reg >= DATA_CHANNEL_1_AND_0 &&
reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2);
/* Poor man's sampling */
uint32_t value = s->regs[reg];
s->regs[reg] = update_channels(s->regs[reg]);
if (breaks_threshold(s, reg)) {
s->regs[INTERRUPT_CONTROL] |= BIT(reg - DATA_CHANNEL_1_AND_0);
qemu_irq_raise(s->irq);
}
return value;
}
static uint64_t aspeed_adc_engine_read(void *opaque, hwaddr addr,
unsigned int size)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(opaque);
int reg = TO_REG(addr);
uint32_t value = 0;
switch (reg) {
case BOUNDS_CHANNEL_8 ... BOUNDS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"bounds register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - BOUNDS_CHANNEL_0);
break;
}
/* fallthrough */
case HYSTERESIS_CHANNEL_8 ... HYSTERESIS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"hysteresis register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0);
break;
}
/* fallthrough */
case BOUNDS_CHANNEL_0 ... BOUNDS_CHANNEL_7:
case HYSTERESIS_CHANNEL_0 ... HYSTERESIS_CHANNEL_7:
case ENGINE_CONTROL:
case INTERRUPT_CONTROL:
case VGA_DETECT_CONTROL:
case CLOCK_CONTROL:
case INTERRUPT_SOURCE:
case COMPENSATING_AND_TRIMMING:
value = s->regs[reg];
break;
case DATA_CHANNEL_9_AND_8 ... DATA_CHANNEL_15_AND_14:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"data register %u invalid, only 0...3 valid\n",
__func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0);
break;
}
/* fallthrough */
case DATA_CHANNEL_1_AND_0 ... DATA_CHANNEL_7_AND_6:
value = read_channel_sample(s, reg);
/* Allow 16-bit reads of the data registers */
if (addr & 0x2) {
assert(size == 2);
value >>= 16;
}
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: 0x%" HWADDR_PRIx "\n",
__func__, s->engine_id, addr);
break;
}
trace_aspeed_adc_engine_read(s->engine_id, addr, value);
return value;
}
static void aspeed_adc_engine_write(void *opaque, hwaddr addr, uint64_t value,
unsigned int size)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(opaque);
int reg = TO_REG(addr);
uint32_t init = 0;
trace_aspeed_adc_engine_write(s->engine_id, addr, value);
switch (reg) {
case ENGINE_CONTROL:
init = !!(value & ASPEED_ADC_ENGINE_EN);
init *= ASPEED_ADC_ENGINE_INIT;
value &= ~ASPEED_ADC_ENGINE_INIT;
value |= init;
value &= ~ASPEED_ADC_ENGINE_AUTO_COMP;
break;
case INTERRUPT_CONTROL:
case VGA_DETECT_CONTROL:
case CLOCK_CONTROL:
break;
case DATA_CHANNEL_9_AND_8 ... DATA_CHANNEL_15_AND_14:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"data register %u invalid, only 0...3 valid\n",
__func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0);
return;
}
/* fallthrough */
case BOUNDS_CHANNEL_8 ... BOUNDS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"bounds register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - BOUNDS_CHANNEL_0);
return;
}
/* fallthrough */
case DATA_CHANNEL_1_AND_0 ... DATA_CHANNEL_7_AND_6:
case BOUNDS_CHANNEL_0 ... BOUNDS_CHANNEL_7:
value &= ASPEED_ADC_LH_MASK;
break;
case HYSTERESIS_CHANNEL_8 ... HYSTERESIS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"hysteresis register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0);
return;
}
/* fallthrough */
case HYSTERESIS_CHANNEL_0 ... HYSTERESIS_CHANNEL_7:
value &= (ASPEED_ADC_HYST_EN | ASPEED_ADC_LH_MASK);
break;
case INTERRUPT_SOURCE:
value &= 0xffff;
break;
case COMPENSATING_AND_TRIMMING:
value &= 0xf;
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: "
"0x%" HWADDR_PRIx " 0x%" PRIx64 "\n",
__func__, s->engine_id, addr, value);
/* Do not update the regs[] array */
return;
}
s->regs[reg] = value;
}
static const MemoryRegionOps aspeed_adc_engine_ops = {
.read = aspeed_adc_engine_read,
.write = aspeed_adc_engine_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 2,
.max_access_size = 4,
.unaligned = false,
},
};
static const uint32_t aspeed_adc_resets[ASPEED_ADC_NR_REGS] = {
[ENGINE_CONTROL] = 0x00000000,
[INTERRUPT_CONTROL] = 0x00000000,
[VGA_DETECT_CONTROL] = 0x0000000f,
[CLOCK_CONTROL] = 0x0000000f,
};
static void aspeed_adc_engine_reset_hold(Object *obj, ResetType type)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(obj);
memcpy(s->regs, aspeed_adc_resets, sizeof(aspeed_adc_resets));
}
static void aspeed_adc_engine_realize(DeviceState *dev, Error **errp)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
g_autofree char *name = g_strdup_printf(TYPE_ASPEED_ADC_ENGINE ".%d",
s->engine_id);
assert(s->engine_id < 2);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_adc_engine_ops, s, name,
ASPEED_ADC_ENGINE_MEMORY_REGION_SIZE);
sysbus_init_mmio(sbd, &s->mmio);
}
static const VMStateDescription vmstate_aspeed_adc_engine = {
.name = TYPE_ASPEED_ADC,
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedADCEngineState, ASPEED_ADC_NR_REGS),
VMSTATE_END_OF_LIST(),
}
};
static const Property aspeed_adc_engine_properties[] = {
DEFINE_PROP_UINT32("engine-id", AspeedADCEngineState, engine_id, 0),
DEFINE_PROP_UINT32("nr-channels", AspeedADCEngineState, nr_channels, 0),
};
static void aspeed_adc_engine_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_adc_engine_realize;
rc->phases.hold = aspeed_adc_engine_reset_hold;
device_class_set_props(dc, aspeed_adc_engine_properties);
dc->desc = "Aspeed Analog-to-Digital Engine";
dc->vmsd = &vmstate_aspeed_adc_engine;
}
static void aspeed_adc_instance_init(Object *obj)
{
AspeedADCState *s = ASPEED_ADC(obj);
AspeedADCClass *aac = ASPEED_ADC_GET_CLASS(obj);
uint32_t nr_channels = ASPEED_ADC_NR_CHANNELS / aac->nr_engines;
for (int i = 0; i < aac->nr_engines; i++) {
AspeedADCEngineState *engine = &s->engines[i];
object_initialize_child(obj, "engine[*]", engine,
TYPE_ASPEED_ADC_ENGINE);
qdev_prop_set_uint32(DEVICE(engine), "engine-id", i);
qdev_prop_set_uint32(DEVICE(engine), "nr-channels", nr_channels);
}
}
static void aspeed_adc_set_irq(void *opaque, int n, int level)
{
AspeedADCState *s = opaque;
AspeedADCClass *aac = ASPEED_ADC_GET_CLASS(s);
uint32_t pending = 0;
/* TODO: update Global IRQ status register on AST2600 (Need specs) */
for (int i = 0; i < aac->nr_engines; i++) {
uint32_t irq_status = s->engines[i].regs[INTERRUPT_CONTROL] & 0xFF;
pending |= irq_status << (i * 8);
}
qemu_set_irq(s->irq, !!pending);
}
static void aspeed_adc_realize(DeviceState *dev, Error **errp)
{
AspeedADCState *s = ASPEED_ADC(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedADCClass *aac = ASPEED_ADC_GET_CLASS(dev);
qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_adc_set_irq,
s, NULL, aac->nr_engines);
sysbus_init_irq(sbd, &s->irq);
memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_ADC,
ASPEED_ADC_MEMORY_REGION_SIZE);
sysbus_init_mmio(sbd, &s->mmio);
for (int i = 0; i < aac->nr_engines; i++) {
Object *eng = OBJECT(&s->engines[i]);
if (!sysbus_realize(SYS_BUS_DEVICE(eng), errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(eng), 0,
qdev_get_gpio_in(DEVICE(sbd), i));
memory_region_add_subregion(&s->mmio,
i * ASPEED_ADC_ENGINE_MEMORY_REGION_SIZE,
&s->engines[i].mmio);
}
}
static void aspeed_adc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedADCClass *aac = ASPEED_ADC_CLASS(klass);
dc->realize = aspeed_adc_realize;
dc->desc = "Aspeed Analog-to-Digital Converter";
aac->nr_engines = 1;
}
static void aspeed_2600_adc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedADCClass *aac = ASPEED_ADC_CLASS(klass);
dc->desc = "ASPEED 2600 ADC Controller";
aac->nr_engines = 2;
}
static void aspeed_1030_adc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedADCClass *aac = ASPEED_ADC_CLASS(klass);
dc->desc = "ASPEED 1030 ADC Controller";
aac->nr_engines = 2;
}
static void aspeed_2700_adc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedADCClass *aac = ASPEED_ADC_CLASS(klass);
dc->desc = "ASPEED 2700 ADC Controller";
aac->nr_engines = 2;
}
static const TypeInfo aspeed_adc_types[] = {
{
.name = TYPE_ASPEED_ADC_ENGINE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedADCEngineState),
.class_init = aspeed_adc_engine_class_init,
},
{
.name = TYPE_ASPEED_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_init = aspeed_adc_instance_init,
.instance_size = sizeof(AspeedADCState),
.class_init = aspeed_adc_class_init,
.class_size = sizeof(AspeedADCClass),
.abstract = true,
},
{
.name = TYPE_ASPEED_1030_ADC,
.parent = TYPE_ASPEED_ADC,
.class_init = aspeed_1030_adc_class_init, /* No change since AST2600 */
},
{
.name = TYPE_ASPEED_2400_ADC,
.parent = TYPE_ASPEED_ADC,
},
{
.name = TYPE_ASPEED_2500_ADC,
.parent = TYPE_ASPEED_ADC,
},
{
.name = TYPE_ASPEED_2600_ADC,
.parent = TYPE_ASPEED_ADC,
.class_init = aspeed_2600_adc_class_init,
},
{
.name = TYPE_ASPEED_2700_ADC,
.parent = TYPE_ASPEED_ADC,
.class_init = aspeed_2700_adc_class_init,
}
};
DEFINE_TYPES(aspeed_adc_types)
hw/adc/meson.build
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system_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_adc.c'))
system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq-xadc.c'))
hw/adc/npcm7xx_adc.c
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/*
* Nuvoton NPCM7xx ADC Module
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "hw/adc/npcm7xx_adc.h"
#include "hw/core/qdev-clock.h"
#include "hw/core/qdev-properties.h"
#include "hw/core/registerfields.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "qemu/units.h"
#include "trace.h"
REG32(NPCM7XX_ADC_CON, 0x0)
REG32(NPCM7XX_ADC_DATA, 0x4)
/* Register field definitions. */
#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
#define NPCM7XX_ADC_CON_INT_EN BIT(21)
#define NPCM7XX_ADC_CON_REFSEL BIT(19)
#define NPCM7XX_ADC_CON_INT BIT(18)
#define NPCM7XX_ADC_CON_EN BIT(17)
#define NPCM7XX_ADC_CON_RST BIT(16)
#define NPCM7XX_ADC_CON_CONV BIT(13)
#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
#define NPCM7XX_ADC_MAX_RESULT 1023
#define NPCM7XX_ADC_DEFAULT_IREF 2000000
#define NPCM7XX_ADC_CONV_CYCLES 20
#define NPCM7XX_ADC_RESET_CYCLES 10
#define NPCM7XX_ADC_R0_INPUT 500000
#define NPCM7XX_ADC_R1_INPUT 1500000
static void npcm7xx_adc_reset(NPCM7xxADCState *s)
{
timer_del(&s->conv_timer);
s->con = 0x000c0001;
s->data = 0x00000000;
}
static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
{
uint32_t result;
result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
if (result > NPCM7XX_ADC_MAX_RESULT) {
result = NPCM7XX_ADC_MAX_RESULT;
}
return result;
}
static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
{
return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
}
static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
uint32_t cycles, uint32_t prescaler)
{
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t ticks = cycles;
int64_t ns;
ticks *= prescaler;
ns = clock_ticks_to_ns(clk, ticks);
ns += now;
timer_mod(timer, ns);
}
static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
{
uint32_t prescaler = npcm7xx_adc_prescaler(s);
npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
prescaler);
}
static void npcm7xx_adc_convert_done(void *opaque)
{
NPCM7xxADCState *s = opaque;
uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
? s->iref : s->vref;
if (input >= NPCM7XX_ADC_NUM_INPUTS) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
__func__, input);
return;
}
s->data = npcm7xx_adc_convert(s->adci[input], ref);
if (s->con & NPCM7XX_ADC_CON_INT_EN) {
s->con |= NPCM7XX_ADC_CON_INT;
qemu_irq_raise(s->irq);
}
s->con &= ~NPCM7XX_ADC_CON_CONV;
}
static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
{
adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
adc->iref);
adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
adc->iref);
}
static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
{
uint32_t old_con = s->con;
/* Write ADC_INT to 1 to clear it */
if (new_con & NPCM7XX_ADC_CON_INT) {
new_con &= ~NPCM7XX_ADC_CON_INT;
qemu_irq_lower(s->irq);
} else if (old_con & NPCM7XX_ADC_CON_INT) {
new_con |= NPCM7XX_ADC_CON_INT;
}
s->con = new_con;
if (s->con & NPCM7XX_ADC_CON_RST) {
npcm7xx_adc_reset(s);
return;
}
if ((s->con & NPCM7XX_ADC_CON_EN)) {
if (s->con & NPCM7XX_ADC_CON_CONV) {
if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
npcm7xx_adc_start_convert(s);
}
} else {
timer_del(&s->conv_timer);
}
}
}
static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
{
uint64_t value = 0;
NPCM7xxADCState *s = opaque;
switch (offset) {
case A_NPCM7XX_ADC_CON:
value = s->con;
break;
case A_NPCM7XX_ADC_DATA:
value = s->data;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
__func__, offset);
break;
}
trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
return value;
}
static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
unsigned size)
{
NPCM7xxADCState *s = opaque;
trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
switch (offset) {
case A_NPCM7XX_ADC_CON:
npcm7xx_adc_write_con(s, v);
break;
case A_NPCM7XX_ADC_DATA:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
__func__, offset);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
__func__, offset);
break;
}
}
static const struct MemoryRegionOps npcm7xx_adc_ops = {
.read = npcm7xx_adc_read,
.write = npcm7xx_adc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
{
NPCM7xxADCState *s = NPCM7XX_ADC(obj);
npcm7xx_adc_reset(s);
}
static void npcm7xx_adc_hold_reset(Object *obj, ResetType type)
{
NPCM7xxADCState *s = NPCM7XX_ADC(obj);
qemu_irq_lower(s->irq);
}
static void npcm7xx_adc_init(Object *obj)
{
NPCM7xxADCState *s = NPCM7XX_ADC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
sysbus_init_irq(sbd, &s->irq);
timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
npcm7xx_adc_convert_done, s);
memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
TYPE_NPCM7XX_ADC, 4 * KiB);
sysbus_init_mmio(sbd, &s->iomem);
s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, 0);
for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
object_property_add_uint32_ptr(obj, "adci[*]",
&s->adci[i], OBJ_PROP_FLAG_READWRITE);
}
object_property_add_uint32_ptr(obj, "vref",
&s->vref, OBJ_PROP_FLAG_WRITE);
npcm7xx_adc_calibrate(s);
}
static const VMStateDescription vmstate_npcm7xx_adc = {
.name = "npcm7xx-adc",
.version_id = 0,
.minimum_version_id = 0,
.fields = (const VMStateField[]) {
VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
VMSTATE_UINT32(con, NPCM7xxADCState),
VMSTATE_UINT32(data, NPCM7xxADCState),
VMSTATE_CLOCK(clock, NPCM7xxADCState),
VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
VMSTATE_UINT32(vref, NPCM7xxADCState),
VMSTATE_UINT32(iref, NPCM7xxADCState),
VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
NPCM7XX_ADC_NUM_CALIB),
VMSTATE_END_OF_LIST(),
},
};
static const Property npcm7xx_timer_properties[] = {
DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
};
static void npcm7xx_adc_class_init(ObjectClass *klass, const void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "NPCM7xx ADC Module";
dc->vmsd = &vmstate_npcm7xx_adc;
rc->phases.enter = npcm7xx_adc_enter_reset;
rc->phases.hold = npcm7xx_adc_hold_reset;
device_class_set_props(dc, npcm7xx_timer_properties);
}
static const TypeInfo npcm7xx_adc_info = {
.name = TYPE_NPCM7XX_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxADCState),
.class_init = npcm7xx_adc_class_init,
.instance_init = npcm7xx_adc_init,
};
static void npcm7xx_adc_register_types(void)
{
type_register_static(&npcm7xx_adc_info);
}
type_init(npcm7xx_adc_register_types);
hw/adc/stm32f2xx_adc.c
+308
View File
@@ -0,0 +1,308 @@
/*
* STM32F2XX ADC
*
* Copyright (c) 2014 Alistair Francis <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/adc/stm32f2xx_adc.h"
#ifndef STM_ADC_ERR_DEBUG
#define STM_ADC_ERR_DEBUG 0
#endif
#define DB_PRINT_L(lvl, fmt, args...) do { \
if (STM_ADC_ERR_DEBUG >= lvl) { \
qemu_log("%s: " fmt, __func__, ## args); \
} \
} while (0)
#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
static void stm32f2xx_adc_reset(DeviceState *dev)
{
STM32F2XXADCState *s = STM32F2XX_ADC(dev);
s->adc_sr = 0x00000000;
s->adc_cr1 = 0x00000000;
s->adc_cr2 = 0x00000000;
s->adc_smpr1 = 0x00000000;
s->adc_smpr2 = 0x00000000;
s->adc_jofr[0] = 0x00000000;
s->adc_jofr[1] = 0x00000000;
s->adc_jofr[2] = 0x00000000;
s->adc_jofr[3] = 0x00000000;
s->adc_htr = 0x00000FFF;
s->adc_ltr = 0x00000000;
s->adc_sqr1 = 0x00000000;
s->adc_sqr2 = 0x00000000;
s->adc_sqr3 = 0x00000000;
s->adc_jsqr = 0x00000000;
s->adc_jdr[0] = 0x00000000;
s->adc_jdr[1] = 0x00000000;
s->adc_jdr[2] = 0x00000000;
s->adc_jdr[3] = 0x00000000;
s->adc_dr = 0x00000000;
}
static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s)
{
/* Attempts to fake some ADC values */
s->adc_dr = s->adc_dr + 7;
switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) {
case 0:
/* 12-bit */
s->adc_dr &= 0xFFF;
break;
case 1:
/* 10-bit */
s->adc_dr &= 0x3FF;
break;
case 2:
/* 8-bit */
s->adc_dr &= 0xFF;
break;
default:
/* 6-bit */
s->adc_dr &= 0x3F;
}
if (s->adc_cr2 & ADC_CR2_ALIGN) {
return (s->adc_dr << 1) & 0xFFF0;
} else {
return s->adc_dr;
}
}
static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr,
unsigned int size)
{
STM32F2XXADCState *s = opaque;
DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
if (addr >= ADC_COMMON_ADDRESS) {
qemu_log_mask(LOG_UNIMP,
"%s: ADC Common Register Unsupported\n", __func__);
}
switch (addr) {
case ADC_SR:
return s->adc_sr;
case ADC_CR1:
return s->adc_cr1;
case ADC_CR2:
return s->adc_cr2 & 0xFFFFFFF;
case ADC_SMPR1:
return s->adc_smpr1;
case ADC_SMPR2:
return s->adc_smpr2;
case ADC_JOFR1:
case ADC_JOFR2:
case ADC_JOFR3:
case ADC_JOFR4:
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
return s->adc_jofr[(addr - ADC_JOFR1) / 4];
case ADC_HTR:
return s->adc_htr;
case ADC_LTR:
return s->adc_ltr;
case ADC_SQR1:
return s->adc_sqr1;
case ADC_SQR2:
return s->adc_sqr2;
case ADC_SQR3:
return s->adc_sqr3;
case ADC_JSQR:
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
return s->adc_jsqr;
case ADC_JDR1:
case ADC_JDR2:
case ADC_JDR3:
case ADC_JDR4:
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
return s->adc_jdr[(addr - ADC_JDR1) / 4] -
s->adc_jofr[(addr - ADC_JDR1) / 4];
case ADC_DR:
if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) {
s->adc_cr2 ^= ADC_CR2_SWSTART;
return stm32f2xx_adc_generate_value(s);
} else {
return 0;
}
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
}
return 0;
}
static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
STM32F2XXADCState *s = opaque;
uint32_t value = (uint32_t) val64;
DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n",
addr, value);
if (addr >= 0x100) {
qemu_log_mask(LOG_UNIMP,
"%s: ADC Common Register Unsupported\n", __func__);
}
switch (addr) {
case ADC_SR:
s->adc_sr &= (value & 0x3F);
break;
case ADC_CR1:
s->adc_cr1 = value;
break;
case ADC_CR2:
s->adc_cr2 = value;
break;
case ADC_SMPR1:
s->adc_smpr1 = value;
break;
case ADC_SMPR2:
s->adc_smpr2 = value;
break;
case ADC_JOFR1:
case ADC_JOFR2:
case ADC_JOFR3:
case ADC_JOFR4:
s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF);
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
break;
case ADC_HTR:
s->adc_htr = value;
break;
case ADC_LTR:
s->adc_ltr = value;
break;
case ADC_SQR1:
s->adc_sqr1 = value;
break;
case ADC_SQR2:
s->adc_sqr2 = value;
break;
case ADC_SQR3:
s->adc_sqr3 = value;
break;
case ADC_JSQR:
s->adc_jsqr = value;
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
break;
case ADC_JDR1:
case ADC_JDR2:
case ADC_JDR3:
case ADC_JDR4:
s->adc_jdr[(addr - ADC_JDR1) / 4] = value;
qemu_log_mask(LOG_UNIMP, "%s: " \
"Injection ADC is not implemented, the registers are " \
"included for compatibility\n", __func__);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
}
}
static const MemoryRegionOps stm32f2xx_adc_ops = {
.read = stm32f2xx_adc_read,
.write = stm32f2xx_adc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
static const VMStateDescription vmstate_stm32f2xx_adc = {
.name = TYPE_STM32F2XX_ADC,
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(adc_sr, STM32F2XXADCState),
VMSTATE_UINT32(adc_cr1, STM32F2XXADCState),
VMSTATE_UINT32(adc_cr2, STM32F2XXADCState),
VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState),
VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState),
VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4),
VMSTATE_UINT32(adc_htr, STM32F2XXADCState),
VMSTATE_UINT32(adc_ltr, STM32F2XXADCState),
VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState),
VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState),
VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState),
VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState),
VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4),
VMSTATE_UINT32(adc_dr, STM32F2XXADCState),
VMSTATE_END_OF_LIST()
}
};
static void stm32f2xx_adc_init(Object *obj)
{
STM32F2XXADCState *s = STM32F2XX_ADC(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
TYPE_STM32F2XX_ADC, 0x100);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
static void stm32f2xx_adc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_legacy_reset(dc, stm32f2xx_adc_reset);
dc->vmsd = &vmstate_stm32f2xx_adc;
}
static const TypeInfo stm32f2xx_adc_info = {
.name = TYPE_STM32F2XX_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(STM32F2XXADCState),
.instance_init = stm32f2xx_adc_init,
.class_init = stm32f2xx_adc_class_init,
};
static void stm32f2xx_adc_register_types(void)
{
type_register_static(&stm32f2xx_adc_info);
}
type_init(stm32f2xx_adc_register_types)
hw/adc/trace-events
+8
View File
@@ -0,0 +1,8 @@
# See docs/devel/tracing.rst for syntax documentation.
# npcm7xx_adc.c
npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
aspeed_adc_engine_read(uint32_t engine_id, uint64_t addr, uint64_t value) "engine[%u] 0x%" PRIx64 " 0x%" PRIx64
aspeed_adc_engine_write(uint32_t engine_id, uint64_t addr, uint64_t value) "engine[%u] 0x%" PRIx64 " 0x%" PRIx64
hw/adc/trace.h
+1
View File
@@ -0,0 +1 @@
#include "trace/trace-hw_adc.h"
hw/adc/zynq-xadc.c
+305
View File
@@ -0,0 +1,305 @@
/*
* ADC registers for Xilinx Zynq Platform
*
* Copyright (c) 2015 Guenter Roeck
* Based on hw/misc/zynq_slcr.c, written by Michal Simek
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/core/irq.h"
#include "hw/adc/zynq-xadc.h"
#include "migration/vmstate.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
enum {
CFG = 0x000 / 4,
INT_STS,
INT_MASK,
MSTS,
CMDFIFO,
RDFIFO,
MCTL,
};
#define CFG_ENABLE BIT(31)
#define CFG_CFIFOTH_SHIFT 20
#define CFG_CFIFOTH_LENGTH 4
#define CFG_DFIFOTH_SHIFT 16
#define CFG_DFIFOTH_LENGTH 4
#define CFG_WEDGE BIT(13)
#define CFG_REDGE BIT(12)
#define CFG_TCKRATE_SHIFT 8
#define CFG_TCKRATE_LENGTH 2
#define CFG_TCKRATE_DIV(x) (0x1 << (x - 1))
#define CFG_IGAP_SHIFT 0
#define CFG_IGAP_LENGTH 5
#define INT_CFIFO_LTH BIT(9)
#define INT_DFIFO_GTH BIT(8)
#define INT_OT BIT(7)
#define INT_ALM_SHIFT 0
#define INT_ALM_LENGTH 7
#define INT_ALM_MASK (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
#define INT_ALL (INT_CFIFO_LTH | INT_DFIFO_GTH | INT_OT | INT_ALM_MASK)
#define MSTS_CFIFO_LVL_SHIFT 16
#define MSTS_CFIFO_LVL_LENGTH 4
#define MSTS_DFIFO_LVL_SHIFT 12
#define MSTS_DFIFO_LVL_LENGTH 4
#define MSTS_CFIFOF BIT(11)
#define MSTS_CFIFOE BIT(10)
#define MSTS_DFIFOF BIT(9)
#define MSTS_DFIFOE BIT(8)
#define MSTS_OT BIT(7)
#define MSTS_ALM_SHIFT 0
#define MSTS_ALM_LENGTH 7
#define MCTL_RESET BIT(4)
#define CMD_NOP 0x00
#define CMD_READ 0x01
#define CMD_WRITE 0x02
static void zynq_xadc_update_ints(ZynqXADCState *s)
{
/* We are fast, commands are actioned instantly so the CFIFO is always
* empty (and below threshold).
*/
s->regs[INT_STS] |= INT_CFIFO_LTH;
if (s->xadc_dfifo_entries >
extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) {
s->regs[INT_STS] |= INT_DFIFO_GTH;
}
qemu_set_irq(s->irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
}
static void zynq_xadc_reset(DeviceState *d)
{
ZynqXADCState *s = ZYNQ_XADC(d);
s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT |
CFG_TCKRATE_DIV(4) << CFG_TCKRATE_SHIFT | CFG_REDGE;
s->regs[INT_STS] = INT_CFIFO_LTH;
s->regs[INT_MASK] = 0xffffffff;
s->regs[CMDFIFO] = 0;
s->regs[RDFIFO] = 0;
s->regs[MCTL] = MCTL_RESET;
memset(s->xadc_regs, 0, sizeof(s->xadc_regs));
memset(s->xadc_dfifo, 0, sizeof(s->xadc_dfifo));
s->xadc_dfifo_entries = 0;
zynq_xadc_update_ints(s);
}
static uint16_t xadc_pop_dfifo(ZynqXADCState *s)
{
uint16_t rv = s->xadc_dfifo[0];
int i;
if (s->xadc_dfifo_entries > 0) {
s->xadc_dfifo_entries--;
}
for (i = 0; i < s->xadc_dfifo_entries; i++) {
s->xadc_dfifo[i] = s->xadc_dfifo[i + 1];
}
s->xadc_dfifo[s->xadc_dfifo_entries] = 0;
zynq_xadc_update_ints(s);
return rv;
}
static void xadc_push_dfifo(ZynqXADCState *s, uint16_t regval)
{
if (s->xadc_dfifo_entries < ZYNQ_XADC_FIFO_DEPTH) {
s->xadc_dfifo[s->xadc_dfifo_entries++] = s->xadc_read_reg_previous;
}
s->xadc_read_reg_previous = regval;
zynq_xadc_update_ints(s);
}
static bool zynq_xadc_check_offset(hwaddr offset, bool rnw)
{
switch (offset) {
case CFG:
case INT_MASK:
case INT_STS:
case MCTL:
return true;
case RDFIFO:
case MSTS:
return rnw; /* read only */
case CMDFIFO:
return !rnw; /* write only */
default:
return false;
}
}
static uint64_t zynq_xadc_read(void *opaque, hwaddr offset, unsigned size)
{
ZynqXADCState *s = opaque;
int reg = offset / 4;
uint32_t rv = 0;
if (!zynq_xadc_check_offset(reg, true)) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid read access to "
"addr %" HWADDR_PRIx "\n", offset);
return 0;
}
switch (reg) {
case CFG:
case INT_MASK:
case INT_STS:
case MCTL:
rv = s->regs[reg];
break;
case MSTS:
rv = MSTS_CFIFOE;
rv |= s->xadc_dfifo_entries << MSTS_DFIFO_LVL_SHIFT;
if (!s->xadc_dfifo_entries) {
rv |= MSTS_DFIFOE;
} else if (s->xadc_dfifo_entries == ZYNQ_XADC_FIFO_DEPTH) {
rv |= MSTS_DFIFOF;
}
break;
case RDFIFO:
rv = xadc_pop_dfifo(s);
break;
}
return rv;
}
static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
ZynqXADCState *s = (ZynqXADCState *)opaque;
int reg = offset / 4;
int xadc_reg;
int xadc_cmd;
int xadc_data;
if (!zynq_xadc_check_offset(reg, false)) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
"to addr %" HWADDR_PRIx "\n", offset);
return;
}
switch (reg) {
case CFG:
s->regs[CFG] = val;
break;
case INT_STS:
s->regs[INT_STS] &= ~val;
break;
case INT_MASK:
s->regs[INT_MASK] = val & INT_ALL;
break;
case CMDFIFO:
xadc_cmd = extract32(val, 26, 4);
xadc_reg = extract32(val, 16, 10);
xadc_data = extract32(val, 0, 16);
if (s->regs[MCTL] & MCTL_RESET) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
"while comm channel held in reset: %" PRIx32 "\n",
(uint32_t) val);
break;
}
if (xadc_reg >= ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
"reg 0x%x\n", xadc_reg);
break;
}
switch (xadc_cmd) {
case CMD_READ:
xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);
break;
case CMD_WRITE:
s->xadc_regs[xadc_reg] = xadc_data;
/* fallthrough */
case CMD_NOP:
xadc_push_dfifo(s, 0);
break;
}
break;
case MCTL:
s->regs[MCTL] = val & 0x00fffeff;
break;
}
zynq_xadc_update_ints(s);
}
static const MemoryRegionOps xadc_ops = {
.read = zynq_xadc_read,
.write = zynq_xadc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void zynq_xadc_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
ZynqXADCState *s = ZYNQ_XADC(obj);
memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",
ZYNQ_XADC_MMIO_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static const VMStateDescription vmstate_zynq_xadc = {
.name = "zynq-xadc",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS),
VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState,
ZYNQ_XADC_NUM_ADC_REGS),
VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState,
ZYNQ_XADC_FIFO_DEPTH),
VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState),
VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState),
VMSTATE_END_OF_LIST()
}
};
static void zynq_xadc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_zynq_xadc;
device_class_set_legacy_reset(dc, zynq_xadc_reset);
}
static const TypeInfo zynq_xadc_info = {
.class_init = zynq_xadc_class_init,
.name = TYPE_ZYNQ_XADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ZynqXADCState),
.instance_init = zynq_xadc_init,
};
static void zynq_xadc_register_types(void)
{
type_register_static(&zynq_xadc_info);
}
type_init(zynq_xadc_register_types)