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Import QEMU upstream snapshot d2e570c

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Upstream: https://gitlab.com/qemu-project/qemu.git

Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
This commit is contained in:
Yaya48
2026-08-31 02:15:30 +02:00
commit cf256aa081
11315 changed files with 3598369 additions and 0 deletions
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hw/sparc/Kconfig
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config SUN4M
bool
default y
depends on SPARC && !SPARC64
imply TCX
imply CG3
select CS4231
select ECCMEMCTL
select EMPTY_SLOT
select UNIMP
select ESCC
select ESP
select FDC_SYSBUS
select SLAVIO
select LANCE
select M48T59
select STP2000
select CHRP_NVRAM
select OR_IRQ
config LEON3
bool
default y
depends on SPARC && !SPARC64
select GRLIB
config GRLIB
bool
select PTIMER
config SLAVIO
bool
select PTIMER
hw/sparc/leon3.c
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/*
* QEMU Leon3 System Emulator
*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "exec/cpu-common.h"
#include "target/sparc/cpu.h"
#include "hw/core/irq.h"
#include "qemu/timer.h"
#include "hw/core/ptimer.h"
#include "hw/core/qdev-properties.h"
#include "system/system.h"
#include "system/qtest.h"
#include "system/reset.h"
#include "hw/core/boards.h"
#include "hw/core/loader.h"
#include "elf.h"
#include "trace.h"
#include "hw/timer/grlib_gptimer.h"
#include "hw/char/grlib_uart.h"
#include "hw/intc/grlib_irqmp.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Default system clock. */
#define CPU_CLK (40 * 1000 * 1000)
#define LEON3_PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
#define MAX_CPUS 4
#define LEON3_UART_OFFSET (0x80000100)
#define LEON3_UART_IRQ (3)
#define LEON3_IRQMP_OFFSET (0x80000200)
#define LEON3_TIMER_OFFSET (0x80000300)
#define LEON3_TIMER_IRQ (6)
#define LEON3_TIMER_COUNT (2)
#define LEON3_APB_PNP_OFFSET (0x800FF000)
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
typedef struct ResetData {
struct CPUResetData {
int id;
SPARCCPU *cpu;
} info[MAX_CPUS];
uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
{
stl_be_p(code++, 0x82100000); /* mov %g0, %g1 */
stl_be_p(code++, 0x84100000); /* mov %g0, %g2 */
stl_be_p(code++, 0x03000000 +
extract32(addr, 10, 22));
/* sethi %hi(addr), %g1 */
stl_be_p(code++, 0x82106000 +
extract32(addr, 0, 10));
/* or %g1, addr, %g1 */
stl_be_p(code++, 0x05000000 +
extract32(val, 10, 22));
/* sethi %hi(val), %g2 */
stl_be_p(code++, 0x8410a000 +
extract32(val, 0, 10));
/* or %g2, val, %g2 */
stl_be_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
return code;
}
/*
* When loading a kernel in RAM the machine is expected to be in a different
* state (eg: initialized by the bootloader). This little code reproduces
* this behavior. Also this code can be executed by the secondary cpus as
* well since it looks at the %asr17 register before doing any
* initialization, it allows to use the same reset address for all the
* cpus.
*/
static void write_bootloader(void *ptr, hwaddr kernel_addr)
{
uint32_t *p = ptr;
uint32_t *sec_cpu_branch_p = NULL;
/* If we are running on a secondary CPU, jump directly to the kernel. */
stl_be_p(p++, 0x85444000); /* rd %asr17, %g2 */
stl_be_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */
stl_be_p(p++, 0x80908000); /* tst %g2 */
/* Filled below. */
sec_cpu_branch_p = p;
stl_be_p(p++, 0x0BADC0DE); /* bne xxx */
stl_be_p(p++, 0x01000000); /* nop */
/* Initialize the UARTs */
/* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
p = gen_store_u32(p, 0x80000108, 3);
/* Initialize the TIMER 0 */
/* *GPTIMER_SCALER_RELOAD = 40 - 1; */
p = gen_store_u32(p, 0x80000304, 39);
/* *GPTIMER0_COUNTER_RELOAD = 0xFFFE; */
p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
/* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */
p = gen_store_u32(p, 0x80000318, 3);
/* Now, the relative branch above can be computed. */
stl_be_p(sec_cpu_branch_p, 0x12800000
+ (p - sec_cpu_branch_p));
/* JUMP to the entry point */
stl_be_p(p++, 0x82100000); /* mov %g0, %g1 */
stl_be_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
/* sethi %hi(kernel_addr), %g1 */
stl_be_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
/* or kernel_addr, %g1 */
stl_be_p(p++, 0x81c04000); /* jmp %g1 */
stl_be_p(p++, 0x01000000); /* nop */
}
static void leon3_cpu_reset(void *opaque)
{
struct CPUResetData *info = (struct CPUResetData *) opaque;
int id = info->id;
ResetData *s = container_of(info, ResetData, info[id]);
CPUState *cpu = CPU(s->info[id].cpu);
CPUSPARCState *env = cpu_env(cpu);
cpu_reset(cpu);
cpu->halted = cpu->cpu_index != 0;
env->pc = s->entry;
env->npc = s->entry + 4;
}
static void leon3_cache_control_int(CPUSPARCState *env)
{
uint32_t state = 0;
if (env->cache_control & CACHE_CTRL_IF) {
/* Instruction cache state */
state = env->cache_control & CACHE_STATE_MASK;
if (state == CACHE_ENABLED) {
state = CACHE_FROZEN;
trace_int_helper_icache_freeze();
}
env->cache_control &= ~CACHE_STATE_MASK;
env->cache_control |= state;
}
if (env->cache_control & CACHE_CTRL_DF) {
/* Data cache state */
state = (env->cache_control >> 2) & CACHE_STATE_MASK;
if (state == CACHE_ENABLED) {
state = CACHE_FROZEN;
trace_int_helper_dcache_freeze();
}
env->cache_control &= ~(CACHE_STATE_MASK << 2);
env->cache_control |= (state << 2);
}
}
static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
CPUState *cpu = env_cpu(env);
grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno);
}
/*
* This device assumes that the incoming 'level' value on the
* qemu_irq is the interrupt number, not just a simple 0/1 level.
*/
static void leon3_set_pil_in(void *opaque, int n, int level)
{
DeviceState *cpu = opaque;
CPUState *cs = CPU(cpu);
CPUSPARCState *env = cpu_env(cs);
uint32_t pil_in = level;
assert(env != NULL);
env->pil_in = pil_in;
if (env->pil_in && (env->interrupt_index == 0 ||
(env->interrupt_index & ~15) == TT_EXTINT)) {
unsigned int i;
for (i = 15; i > 0; i--) {
if (env->pil_in & (1 << i)) {
int old_interrupt = env->interrupt_index;
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
trace_leon3_set_irq(i);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data)
{
cpu->halted = 0;
}
static void leon3_start_cpu(void *opaque, int n, int level)
{
DeviceState *cpu = opaque;
CPUState *cs = CPU(cpu);
assert(level == 1);
async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL);
}
static void leon3_irq_manager(CPUSPARCState *env, int intno)
{
leon3_irq_ack(env, intno);
leon3_cache_control_int(env);
}
static void leon3_generic_hw_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME;
const char *kernel_filename = machine->kernel_filename;
SPARCCPU *cpu;
CPUSPARCState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret;
char *filename;
int bios_size;
int prom_size;
ResetData *reset_info;
DeviceState *dev, *irqmpdev;
int i;
AHBPnp *ahb_pnp;
APBPnp *apb_pnp;
reset_info = g_malloc0(sizeof(ResetData));
for (i = 0; i < machine->smp.cpus; i++) {
/* Init CPU */
cpu = SPARC_CPU(object_new(machine->cpu_type));
qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1);
qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1);
qdev_realize(DEVICE(cpu), NULL, &error_fatal);
env = &cpu->env;
cpu_sparc_set_id(env, i);
/* Reset data */
reset_info->info[i].id = i;
reset_info->info[i].cpu = cpu;
qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]);
}
ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
GRLIB_CPU_AREA);
apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
/* Allocate IRQ manager */
irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus,
&error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
for (i = 0; i < machine->smp.cpus; i++) {
cpu = reset_info->info[i].cpu;
env = &cpu->env;
qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i,
qdev_get_gpio_in_named(DEVICE(cpu),
"start_cpu", 0));
qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu),
"pil", 0));
env->irq_manager = irqmpdev;
env->qemu_irq_ack = leon3_irq_manager;
}
sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
2, 0, GRLIB_APBIO_AREA);
/* Allocate RAM */
if (ram_size > 1 * GiB) {
error_report("Too much memory for this machine: %" PRId64 "MB,"
" maximum 1G",
ram_size / MiB);
exit(1);
}
memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
machine->ram);
/* Allocate BIOS */
prom_size = 8 * MiB;
memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = get_image_size(filename, NULL);
} else {
bios_size = -1;
}
if (bios_size > prom_size) {
error_report("could not load prom '%s': file too big", filename);
exit(1);
}
if (bios_size > 0) {
ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size, NULL);
if (ret < 0 || ret > prom_size) {
error_report("could not load prom '%s'", filename);
exit(1);
}
} else if (kernel_filename == NULL && !qtest_enabled()) {
error_report("Can't read bios image '%s'", filename
? filename
: LEON3_PROM_FILENAME);
exit(1);
}
g_free(filename);
/* Can directly load an application. */
if (kernel_filename != NULL) {
long kernel_size;
uint64_t entry;
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
&entry, NULL, NULL, NULL,
ELFDATA2MSB, EM_SPARC, 0, 0);
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename, NULL, &entry,
NULL, NULL, NULL);
}
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
if (bios_size <= 0) {
/*
* If there is no bios/monitor just start the application but put
* the machine in an initialized state through a little
* bootloader.
*/
write_bootloader(memory_region_get_ram_ptr(prom), entry);
reset_info->entry = LEON3_PROM_OFFSET;
for (i = 0; i < machine->smp.cpus; i++) {
reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET;
reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4;
}
}
}
/* Allocate timers */
dev = qdev_new(TYPE_GRLIB_GPTIMER);
qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
for (i = 0; i < LEON3_TIMER_COUNT; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i));
}
grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
/* Allocate uart */
dev = qdev_new(TYPE_GRLIB_APB_UART);
qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ));
grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
LEON3_UART_IRQ, GRLIB_APBIO_AREA);
}
static void leon3_generic_machine_init(MachineClass *mc)
{
mc->desc = "Leon-3 generic";
mc->init = leon3_generic_hw_init;
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
mc->default_ram_id = "leon3.ram";
mc->max_cpus = MAX_CPUS;
}
DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
hw/sparc/meson.build
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sparc_ss = ss.source_set()
sparc_ss.add(when: 'CONFIG_LEON3', if_true: files('leon3.c'))
sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m.c'))
sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m_iommu.c'))
hw_arch += {'sparc': sparc_ss}
hw/sparc/sun4m.c
+1488
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File diff suppressed because it is too large Load Diff
hw/sparc/sun4m_iommu.c
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/*
* QEMU Sun4m iommu emulation
*
* Copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/core/irq.h"
#include "hw/core/qdev-properties.h"
#include "hw/sparc/sun4m_iommu.h"
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "system/address-spaces.h"
#include "trace.h"
/*
* I/O MMU used by Sun4m systems
*
* Chipset docs:
* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
*/
#define IOMMU_CTRL (0x0000 >> 2)
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK 0x0000001d
#define IOMMU_BASE (0x0004 >> 2)
#define IOMMU_BASE_MASK 0x07fffc00
#define IOMMU_TLBFLUSH (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff
#define IOMMU_PGFLUSH (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK 0xffffffff
#define IOMMU_AFSR (0x1000 >> 2)
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
transaction */
#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
12.8 us. */
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
acknowledge */
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
hardware */
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK 0xff0fffff
#define IOMMU_AFAR (0x1004 >> 2)
#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK 0x801f000f
#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
produced by this device as pure
physical. */
#define IOMMU_SBCFG_MASK 0x00010003
#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK 0x001f0000
#define IOMMU_MID 0x00000008
#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
#define IOMMU_MASK_ID_MASK 0x00ffffff
#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
/* The format of an iopte in the page tables */
#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
#define IOMMU_PAGE_SHIFT 12
#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
IOMMUState *s = opaque;
hwaddr saddr;
uint32_t ret;
saddr = addr >> 2;
switch (saddr) {
default:
ret = s->regs[saddr];
break;
case IOMMU_AFAR:
case IOMMU_AFSR:
ret = s->regs[saddr];
qemu_irq_lower(s->irq);
break;
}
trace_sun4m_iommu_mem_readl(saddr, ret);
return ret;
}
static void iommu_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IOMMUState *s = opaque;
hwaddr saddr;
saddr = addr >> 2;
trace_sun4m_iommu_mem_writel(saddr, val);
switch (saddr) {
case IOMMU_CTRL:
switch (val & IOMMU_CTRL_RNGE) {
case IOMMU_RNGE_16MB:
s->iostart = 0xffffffffff000000ULL;
break;
case IOMMU_RNGE_32MB:
s->iostart = 0xfffffffffe000000ULL;
break;
case IOMMU_RNGE_64MB:
s->iostart = 0xfffffffffc000000ULL;
break;
case IOMMU_RNGE_128MB:
s->iostart = 0xfffffffff8000000ULL;
break;
case IOMMU_RNGE_256MB:
s->iostart = 0xfffffffff0000000ULL;
break;
case IOMMU_RNGE_512MB:
s->iostart = 0xffffffffe0000000ULL;
break;
case IOMMU_RNGE_1GB:
s->iostart = 0xffffffffc0000000ULL;
break;
default:
case IOMMU_RNGE_2GB:
s->iostart = 0xffffffff80000000ULL;
break;
}
trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
break;
case IOMMU_BASE:
s->regs[saddr] = val & IOMMU_BASE_MASK;
break;
case IOMMU_TLBFLUSH:
trace_sun4m_iommu_mem_writel_tlbflush(val);
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
break;
case IOMMU_PGFLUSH:
trace_sun4m_iommu_mem_writel_pgflush(val);
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
break;
case IOMMU_AFAR:
s->regs[saddr] = val;
qemu_irq_lower(s->irq);
break;
case IOMMU_AER:
s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
break;
case IOMMU_AFSR:
s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
qemu_irq_lower(s->irq);
break;
case IOMMU_SBCFG0:
case IOMMU_SBCFG1:
case IOMMU_SBCFG2:
case IOMMU_SBCFG3:
s->regs[saddr] = val & IOMMU_SBCFG_MASK;
break;
case IOMMU_ARBEN:
/* XXX implement SBus probing: fault when reading unmapped
addresses, fault cause and address stored to MMU/IOMMU */
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
break;
case IOMMU_MASK_ID:
s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
break;
default:
s->regs[saddr] = val;
break;
}
}
static const MemoryRegionOps iommu_mem_ops = {
.read = iommu_mem_read,
.write = iommu_mem_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
uint32_t ret;
hwaddr iopte;
hwaddr pa = addr;
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
ret = address_space_ldl_be(&address_space_memory, iopte,
MEMTXATTRS_UNSPECIFIED, NULL);
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
return ret;
}
static hwaddr iommu_translate_pa(hwaddr addr,
uint32_t pte)
{
hwaddr pa;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
trace_sun4m_iommu_translate_pa(addr, pa, pte);
return pa;
}
static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
int is_write)
{
trace_sun4m_iommu_bad_addr(addr);
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
IOMMU_AFSR_FAV;
if (!is_write) {
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
}
s->regs[IOMMU_AFAR] = addr;
qemu_irq_raise(s->irq);
}
/* Called from RCU critical section */
static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
hwaddr addr,
IOMMUAccessFlags flags,
int iommu_idx)
{
IOMMUState *is = container_of(iommu, IOMMUState, iommu);
hwaddr page, pa;
int is_write = (flags & IOMMU_WO) ? 1 : 0;
uint32_t pte;
IOMMUTLBEntry ret = {
.target_as = &address_space_memory,
.iova = 0,
.translated_addr = 0,
.addr_mask = ~(hwaddr)0,
.perm = IOMMU_NONE,
};
page = addr & IOMMU_PAGE_MASK;
pte = iommu_page_get_flags(is, page);
if (!(pte & IOPTE_VALID)) {
iommu_bad_addr(is, page, is_write);
return ret;
}
pa = iommu_translate_pa(addr, pte);
if (is_write && !(pte & IOPTE_WRITE)) {
iommu_bad_addr(is, page, is_write);
return ret;
}
if (pte & IOPTE_WRITE) {
ret.perm = IOMMU_RW;
} else {
ret.perm = IOMMU_RO;
}
ret.iova = page;
ret.translated_addr = pa;
ret.addr_mask = ~IOMMU_PAGE_MASK;
return ret;
}
static const VMStateDescription vmstate_iommu = {
.name = "iommu",
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
VMSTATE_UINT64(iostart, IOMMUState),
VMSTATE_END_OF_LIST()
}
};
static void iommu_reset(DeviceState *d)
{
IOMMUState *s = SUN4M_IOMMU(d);
memset(s->regs, 0, IOMMU_NREGS * 4);
s->iostart = 0;
s->regs[IOMMU_CTRL] = s->version;
s->regs[IOMMU_ARBEN] = IOMMU_MID;
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
}
static void iommu_realize(DeviceState *ds, Error **errp)
{
IOMMUState *s = SUN4M_IOMMU(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
Object *obj = OBJECT(ds);
memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
TYPE_SUN4M_IOMMU_MEMORY_REGION, obj,
"iommu-sun4m", UINT64_MAX);
address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
IOMMU_NREGS * sizeof(uint32_t));
sysbus_init_mmio(dev, &s->iomem);
}
static const Property iommu_properties[] = {
DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
};
static void iommu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_legacy_reset(dc, iommu_reset);
dc->realize = iommu_realize;
dc->vmsd = &vmstate_iommu;
device_class_set_props(dc, iommu_properties);
}
static const TypeInfo iommu_info = {
.name = TYPE_SUN4M_IOMMU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IOMMUState),
.class_init = iommu_class_init,
};
static void sun4m_iommu_memory_region_class_init(ObjectClass *klass,
const void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
imrc->translate = sun4m_translate_iommu;
}
static const TypeInfo sun4m_iommu_memory_region_info = {
.parent = TYPE_IOMMU_MEMORY_REGION,
.name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
.class_init = sun4m_iommu_memory_region_class_init,
};
static void iommu_register_types(void)
{
type_register_static(&iommu_info);
type_register_static(&sun4m_iommu_memory_region_info);
}
type_init(iommu_register_types)
hw/sparc/trace-events
+21
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@@ -0,0 +1,21 @@
# See docs/devel/tracing.rst for syntax documentation.
# sun4m.c
sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
# sun4m_iommu.c
sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x"
sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x"
sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = 0x%"PRIx64
sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush 0x%x"
sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush 0x%x"
sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr 0x%"PRIx64" => pte 0x%"PRIx64", *pte = 0x%x"
sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva 0x%"PRIx64" => pa 0x%"PRIx64" iopte = 0x%x"
sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
# leon3.c
leon3_set_irq(int intno) "Set CPU IRQ %d"
leon3_reset_irq(int intno) "Reset CPU IRQ %d"
int_helper_icache_freeze(void) "Instruction cache: freeze"
int_helper_dcache_freeze(void) "Data cache: freeze"
hw/sparc/trace.h
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#include "trace/trace-hw_sparc.h"