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Import QEMU upstream snapshot d2e570c

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Upstream: https://gitlab.com/qemu-project/qemu.git

Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
This commit is contained in:
Yaya48
2026-08-31 02:15:30 +02:00
commit cf256aa081
11315 changed files with 3598369 additions and 0 deletions
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include/hw/timer/a9gtimer.h
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/*
* Global peripheral timer block for ARM A9MP
*
* (C) 2013 Xilinx Inc.
*
* Written by François LEGAL
* Written by Peter Crosthwaite <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef A9GTIMER_H
#define A9GTIMER_H
#include "hw/core/sysbus.h"
#include "qom/object.h"
#define A9_GTIMER_MAX_CPUS 4
#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
OBJECT_DECLARE_SIMPLE_TYPE(A9GTimerState, A9_GTIMER)
#define R_COUNTER_LO 0x00
#define R_COUNTER_HI 0x04
#define R_CONTROL 0x08
#define R_CONTROL_TIMER_ENABLE (1 << 0)
#define R_CONTROL_COMP_ENABLE (1 << 1)
#define R_CONTROL_IRQ_ENABLE (1 << 2)
#define R_CONTROL_AUTO_INCREMENT (1 << 3)
#define R_CONTROL_PRESCALER_SHIFT 8
#define R_CONTROL_PRESCALER_LEN 8
#define R_CONTROL_PRESCALER_MASK (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
R_CONTROL_PRESCALER_SHIFT)
#define R_CONTROL_BANKED (R_CONTROL_COMP_ENABLE | \
R_CONTROL_IRQ_ENABLE | \
R_CONTROL_AUTO_INCREMENT)
#define R_CONTROL_NEEDS_SYNC (R_CONTROL_TIMER_ENABLE | \
R_CONTROL_PRESCALER_MASK)
#define R_INTERRUPT_STATUS 0x0C
#define R_COMPARATOR_LO 0x10
#define R_COMPARATOR_HI 0x14
#define R_AUTO_INCREMENT 0x18
typedef struct A9GTimerPerCPU A9GTimerPerCPU;
struct A9GTimerPerCPU {
A9GTimerState *parent;
uint32_t control; /* only per cpu banked bits valid */
uint64_t compare;
uint32_t status;
uint32_t inc;
MemoryRegion iomem;
qemu_irq irq; /* PPI interrupts */
};
struct A9GTimerState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
/* static props */
uint32_t num_cpu;
QEMUTimer *timer;
uint64_t counter; /* current timer value */
uint64_t ref_counter;
uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
uint32_t control; /* only non per cpu banked bits valid */
A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
};
typedef struct A9GTimerUpdate {
uint64_t now;
uint64_t new;
} A9GTimerUpdate;
#endif /* A9GTIMER_H */
include/hw/timer/allwinner-a10-pit.h
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#ifndef ALLWINNER_A10_PIT_H
#define ALLWINNER_A10_PIT_H
#include "hw/core/ptimer.h"
#include "hw/core/sysbus.h"
#include "qom/object.h"
#define TYPE_AW_A10_PIT "allwinner-A10-timer"
OBJECT_DECLARE_SIMPLE_TYPE(AwA10PITState, AW_A10_PIT)
#define AW_A10_PIT_TIMER_NR 6
#define AW_A10_PIT_TIMER_IRQ 0x1
#define AW_A10_PIT_WDOG_IRQ 0x100
#define AW_A10_PIT_TIMER_IRQ_EN 0
#define AW_A10_PIT_TIMER_IRQ_ST 0x4
#define AW_A10_PIT_TIMER_CONTROL 0x0
#define AW_A10_PIT_TIMER_EN 0x1
#define AW_A10_PIT_TIMER_RELOAD 0x2
#define AW_A10_PIT_TIMER_MODE 0x80
#define AW_A10_PIT_TIMER_INTERVAL 0x4
#define AW_A10_PIT_TIMER_COUNT 0x8
#define AW_A10_PIT_WDOG_CONTROL 0x90
#define AW_A10_PIT_WDOG_MODE 0x94
#define AW_A10_PIT_COUNT_CTL 0xa0
#define AW_A10_PIT_COUNT_RL_EN 0x2
#define AW_A10_PIT_COUNT_CLR_EN 0x1
#define AW_A10_PIT_COUNT_LO 0xa4
#define AW_A10_PIT_COUNT_HI 0xa8
#define AW_A10_PIT_TIMER_BASE 0x10
#define AW_A10_PIT_TIMER_BASE_END \
(AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
#define AW_A10_PIT_DEFAULT_CLOCK 0x4
typedef struct AwA10TimerContext {
AwA10PITState *container;
int index;
} AwA10TimerContext;
struct AwA10PITState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq irq[AW_A10_PIT_TIMER_NR];
ptimer_state * timer[AW_A10_PIT_TIMER_NR];
AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
MemoryRegion iomem;
uint32_t clk_freq[4];
uint32_t irq_enable;
uint32_t irq_status;
uint32_t control[AW_A10_PIT_TIMER_NR];
uint32_t interval[AW_A10_PIT_TIMER_NR];
uint32_t count[AW_A10_PIT_TIMER_NR];
uint32_t watch_dog_mode;
uint32_t watch_dog_control;
uint32_t count_lo;
uint32_t count_hi;
uint32_t count_ctl;
};
#endif
include/hw/timer/arm_mptimer.h
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/*
* Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
*
* Copyright (c) 2006-2007 CodeSourcery.
* Copyright (c) 2011 Linaro Limited
* Written by Paul Brook, Peter Maydell
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_TIMER_ARM_MPTIMER_H
#define HW_TIMER_ARM_MPTIMER_H
#include "hw/core/sysbus.h"
#include "qom/object.h"
#define ARM_MPTIMER_MAX_CPUS 4
/* State of a single timer or watchdog block */
typedef struct {
uint32_t control;
uint32_t status;
struct ptimer_state *timer;
qemu_irq irq;
MemoryRegion iomem;
} TimerBlock;
#define TYPE_ARM_MPTIMER "arm_mptimer"
OBJECT_DECLARE_SIMPLE_TYPE(ARMMPTimerState, ARM_MPTIMER)
struct ARMMPTimerState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t num_cpu;
TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS];
MemoryRegion iomem;
};
#endif
include/hw/timer/armv7m_systick.h
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/*
* ARMv7M SysTick timer
*
* Copyright (c) 2006-2007 CodeSourcery.
* Written by Paul Brook
* Copyright (c) 2017 Linaro Ltd
* Written by Peter Maydell
*
* This code is licensed under the GPL (version 2 or later).
*/
#ifndef HW_TIMER_ARMV7M_SYSTICK_H
#define HW_TIMER_ARMV7M_SYSTICK_H
#include "hw/core/sysbus.h"
#include "qom/object.h"
#include "hw/core/ptimer.h"
#include "hw/core/clock.h"
#define TYPE_SYSTICK "armv7m_systick"
OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
/*
* QEMU interface:
* + sysbus MMIO region 0 is the register interface (covering
* the registers which are mapped at address 0xE000E010)
* + sysbus IRQ 0 is the interrupt line to the NVIC
* + Clock input "refclk" is the external reference clock
* (used when SYST_CSR.CLKSOURCE == 0)
* + Clock input "cpuclk" is the main CPU clock
* (used when SYST_CSR.CLKSOURCE == 1)
*/
struct SysTickState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t control;
uint32_t reload;
int64_t tick;
ptimer_state *ptimer;
MemoryRegion iomem;
qemu_irq irq;
Clock *refclk;
Clock *cpuclk;
};
#endif
include/hw/timer/aspeed_timer.h
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/*
* ASPEED AST2400 Timer
*
* Andrew Jeffery <[email protected]>
*
* Copyright (C) 2016 IBM Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <https://www.gnu.org/licenses/>.
*/
#ifndef ASPEED_TIMER_H
#define ASPEED_TIMER_H
#include "qemu/timer.h"
#include "hw/misc/aspeed_scu.h"
#include "qom/object.h"
#define TYPE_ASPEED_TIMER "aspeed.timer"
OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
#define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030"
#define TYPE_ASPEED_2700_TIMER TYPE_ASPEED_TIMER "-ast2700"
#define ASPEED_TIMER_NR_TIMERS 8
typedef struct AspeedTimer {
qemu_irq irq;
uint8_t id;
QEMUTimer timer;
/**
* Track the line level as the ASPEED timers implement edge triggered
* interrupts, signalling with both the rising and falling edge.
*/
int32_t level;
uint32_t reload;
uint32_t match[2];
uint64_t start;
} AspeedTimer;
struct AspeedTimerCtrlState {
/*< private >*/
SysBusDevice parent;
/*< public >*/
MemoryRegion iomem;
uint32_t ctrl;
uint32_t ctrl2;
uint32_t ctrl3;
uint32_t irq_sts;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
};
struct AspeedTimerClass {
SysBusDeviceClass parent_class;
uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset);
void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value);
};
#endif /* ASPEED_TIMER_H */
include/hw/timer/avr_timer16.h
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/*
* AVR 16-bit timer
*
* Copyright (c) 2018 University of Kent
* Author: Ed Robbins
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
/*
* Driver for 16 bit timers on 8 bit AVR devices.
* Note:
* On ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
*/
#ifndef HW_TIMER_AVR_TIMER16_H
#define HW_TIMER_AVR_TIMER16_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
enum NextInterrupt {
OVERFLOW,
COMPA,
COMPB,
COMPC,
CAPT
};
#define TYPE_AVR_TIMER16 "avr-timer16"
OBJECT_DECLARE_SIMPLE_TYPE(AVRTimer16State, AVR_TIMER16)
struct AVRTimer16State {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion iomem;
MemoryRegion imsk_iomem;
MemoryRegion ifr_iomem;
QEMUTimer *timer;
qemu_irq capt_irq;
qemu_irq compa_irq;
qemu_irq compb_irq;
qemu_irq compc_irq;
qemu_irq ovf_irq;
bool enabled;
/* registers */
uint8_t cra;
uint8_t crb;
uint8_t crc;
uint8_t cntl;
uint8_t cnth;
uint8_t icrl;
uint8_t icrh;
uint8_t ocral;
uint8_t ocrah;
uint8_t ocrbl;
uint8_t ocrbh;
uint8_t ocrcl;
uint8_t ocrch;
/*
* Reads and writes to CNT and ICR utilise a bizarre temporary
* register, which we emulate
*/
uint8_t rtmp;
uint8_t imsk;
uint8_t ifr;
uint8_t id;
uint64_t cpu_freq_hz;
uint64_t freq_hz;
uint64_t period_ns;
uint64_t reset_time_ns;
enum NextInterrupt next_interrupt;
};
#endif /* HW_TIMER_AVR_TIMER16_H */
include/hw/timer/bcm2835_systmr.h
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/*
* BCM2835 SYS timer emulation
*
* Copyright (c) 2019 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef BCM2835_SYSTMR_H
#define BCM2835_SYSTMR_H
#include "hw/core/sysbus.h"
#include "hw/core/irq.h"
#include "qemu/timer.h"
#include "qom/object.h"
#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
#define BCM2835_SYSTIMER_COUNT 4
typedef struct {
unsigned id;
QEMUTimer timer;
qemu_irq irq;
BCM2835SystemTimerState *state;
} BCM2835SystemTimerCompare;
struct BCM2835SystemTimerState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
struct {
uint32_t ctrl_status;
uint32_t compare[BCM2835_SYSTIMER_COUNT];
} reg;
BCM2835SystemTimerCompare tmr[BCM2835_SYSTIMER_COUNT];
};
#endif
include/hw/timer/cadence_ttc.h
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/*
* Xilinx Zynq cadence TTC model
*
* Copyright (c) 2011 Xilinx Inc.
* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
* Copyright (c) 2012 PetaLogix Pty Ltd.
* Written By Haibing Ma
* M. Habib
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_TIMER_CADENCE_TTC_H
#define HW_TIMER_CADENCE_TTC_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
typedef struct {
QEMUTimer *timer;
int freq;
uint32_t reg_clock;
uint32_t reg_count;
uint32_t reg_value;
uint16_t reg_interval;
uint16_t reg_match[3];
uint32_t reg_intr;
uint32_t reg_intr_en;
uint32_t reg_event_ctrl;
uint32_t reg_event;
uint64_t cpu_time;
unsigned int cpu_time_valid;
qemu_irq irq;
} CadenceTimerState;
#define TYPE_CADENCE_TTC "cadence_ttc"
OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
struct CadenceTTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
CadenceTimerState timer[3];
};
#endif
include/hw/timer/cmsdk-apb-dualtimer.h
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/*
* ARM CMSDK APB dual-timer emulation
*
* Copyright (c) 2018 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "APB dual-input timer" which is part of the Cortex-M
* System Design Kit (CMSDK) and documented in the Cortex-M System
* Design Kit Technical Reference Manual (ARM DDI0479C):
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
*
* QEMU interface:
* + Clock input "TIMCLK": clock (for both timers)
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: combined timer interrupt TIMINTC
* + sysbus IRO 1: timer block 1 interrupt TIMINT1
* + sysbus IRQ 2: timer block 2 interrupt TIMINT2
*/
#ifndef CMSDK_APB_DUALTIMER_H
#define CMSDK_APB_DUALTIMER_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "hw/core/clock.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER)
/* One of the two identical timer modules in the dual-timer module */
typedef struct CMSDKAPBDualTimerModule {
CMSDKAPBDualTimer *parent;
struct ptimer_state *timer;
qemu_irq timerint;
/*
* We must track the guest LOAD and VALUE register state by hand
* rather than leaving this state only in the ptimer limit/count,
* because if CONTROL.SIZE is 0 then only the low 16 bits of the
* counter actually counts, but the high half is still guest
* accessible.
*/
uint32_t load;
uint32_t value;
uint32_t control;
uint32_t intstatus;
} CMSDKAPBDualTimerModule;
#define CMSDK_APB_DUALTIMER_NUM_MODULES 2
struct CMSDKAPBDualTimer {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq timerintc;
Clock *timclk;
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
uint32_t timeritcr;
uint32_t timeritop;
};
#endif
include/hw/timer/cmsdk-apb-timer.h
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/*
* ARM CMSDK APB timer emulation
*
* Copyright (c) 2017 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
#ifndef CMSDK_APB_TIMER_H
#define CMSDK_APB_TIMER_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "hw/core/clock.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
/*
* QEMU interface:
* + Clock input "pclk": clock for the timer
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: timer interrupt TIMERINT
*/
struct CMSDKAPBTimer {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq timerint;
struct ptimer_state *timer;
Clock *pclk;
uint32_t ctrl;
uint32_t value;
uint32_t reload;
uint32_t intstatus;
};
#endif
include/hw/timer/digic-timer.h
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/*
* Canon DIGIC timer block declarations.
*
* Copyright (C) 2013 Antony Pavlov <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef HW_TIMER_DIGIC_TIMER_H
#define HW_TIMER_DIGIC_TIMER_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "qom/object.h"
#define TYPE_DIGIC_TIMER "digic-timer"
OBJECT_DECLARE_SIMPLE_TYPE(DigicTimerState, DIGIC_TIMER)
#define DIGIC_TIMER_CONTROL 0x00
#define DIGIC_TIMER_CONTROL_RST 0x80000000
#define DIGIC_TIMER_CONTROL_EN 0x00000001
#define DIGIC_TIMER_RELVALUE 0x08
#define DIGIC_TIMER_VALUE 0x0c
struct DigicTimerState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
ptimer_state *ptimer;
uint32_t control;
uint32_t relvalue;
};
#endif /* HW_TIMER_DIGIC_TIMER_H */
include/hw/timer/grlib_gptimer.h
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/*
* QEMU GRLIB GPTimer
*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef GRLIB_GPTIMER_H
#define GRLIB_GPTIMER_H
#define TYPE_GRLIB_GPTIMER "grlib-gptimer"
#endif
include/hw/timer/hpet.h
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/*
* QEMU Emulated HPET support
*
* Copyright IBM, Corp. 2008
*
* Authors:
* Beth Kon <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
*/
#ifndef HW_HPET_H
#define HW_HPET_H
#include "qom/object.h"
#define HPET_BASE 0xfed00000
#define HPET_LEN 0x400
#define HPET_CLK_PERIOD 10 /* 10 ns*/
#define FS_PER_NS 1000000 /* 1000000 femtoseconds == 1 ns */
#define HPET_MIN_TIMERS 3
#define HPET_MAX_TIMERS 24
#define HPET_NUM_IRQ_ROUTES 32
#define HPET_LEGACY_PIT_INT 0
#define HPET_LEGACY_RTC_INT 1
#define HPET_CFG_ENABLE 0x001
#define HPET_CFG_LEGACY 0x002
#define HPET_ID 0x000
#define HPET_PERIOD 0x004
#define HPET_CFG 0x010
#define HPET_STATUS 0x020
#define HPET_COUNTER 0x0f0
#define HPET_TN_CFG 0x000
#define HPET_TN_CMP 0x008
#define HPET_TN_ROUTE 0x010
#define HPET_CFG_WRITE_MASK 0x3
#define HPET_ID_NUM_TIM_SHIFT 8
#define HPET_ID_NUM_TIM_MASK 0x1f00
#define HPET_TN_TYPE_LEVEL 0x002
#define HPET_TN_ENABLE 0x004
#define HPET_TN_PERIODIC 0x008
#define HPET_TN_PERIODIC_CAP 0x010
#define HPET_TN_SIZE_CAP 0x020
#define HPET_TN_SETVAL 0x040
#define HPET_TN_32BIT 0x100
#define HPET_TN_INT_ROUTE_MASK 0x3e00
#define HPET_TN_FSB_ENABLE 0x4000
#define HPET_TN_FSB_CAP 0x8000
#define HPET_TN_CFG_WRITE_MASK 0x7f4e
#define HPET_TN_INT_ROUTE_SHIFT 9
#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
struct hpet_fw_entry
{
uint32_t event_timer_block_id;
uint64_t address;
uint16_t min_tick;
uint8_t page_prot;
} QEMU_PACKED;
struct hpet_fw_config
{
uint8_t count;
struct hpet_fw_entry hpet[8];
} QEMU_PACKED;
extern struct hpet_fw_config hpet_fw_cfg;
#define TYPE_HPET "hpet"
#define HPET_INTCAP "hpet-intcap"
static inline bool hpet_find(void)
{
return object_resolve_path_type("", TYPE_HPET, NULL);
}
#endif
include/hw/timer/i8254.h
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/*
* QEMU 8253/8254 interval timer emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_I8254_H
#define HW_I8254_H
#include "hw/core/qdev-properties.h"
#include "hw/isa/isa.h"
#include "qapi/error.h"
#include "qom/object.h"
#define PIT_FREQ 1193182
typedef struct PITChannelInfo {
int gate;
int mode;
int initial_count;
int out;
} PITChannelInfo;
#define TYPE_PIT_COMMON "pit-common"
OBJECT_DECLARE_TYPE(PITCommonState, PITCommonClass, PIT_COMMON)
#define TYPE_I8254 "isa-pit"
#define TYPE_KVM_I8254 "kvm-pit"
static inline ISADevice *i8254_pit_init(ISABus *bus, int base, int isa_irq,
qemu_irq alt_irq)
{
DeviceState *dev;
ISADevice *d;
d = isa_new(TYPE_I8254);
dev = DEVICE(d);
qdev_prop_set_uint32(dev, "iobase", base);
isa_realize_and_unref(d, bus, &error_fatal);
qdev_connect_gpio_out(dev, 0,
isa_irq >= 0 ? isa_bus_get_irq(bus, isa_irq)
: alt_irq);
return d;
}
static inline ISADevice *kvm_pit_init(ISABus *bus, int base)
{
DeviceState *dev;
ISADevice *d;
d = isa_new(TYPE_KVM_I8254);
dev = DEVICE(d);
qdev_prop_set_uint32(dev, "iobase", base);
isa_realize_and_unref(d, bus, &error_fatal);
return d;
}
void pit_set_gate(PITCommonState *pit, int channel, int val);
void pit_get_channel_info(PITCommonState *pit, int channel, PITChannelInfo *info);
#endif /* HW_I8254_H */
include/hw/timer/i8254_internal.h
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/*
* QEMU 8253/8254 - internal interfaces
*
* Copyright (c) 2011 Jan Kiszka, Siemens AG
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef QEMU_I8254_INTERNAL_H
#define QEMU_I8254_INTERNAL_H
#include "hw/isa/isa.h"
#include "hw/timer/i8254.h"
#include "qemu/timer.h"
typedef struct PITChannelState {
int count; /* can be 65536 */
uint16_t latched_count;
uint8_t count_latched;
uint8_t status_latched;
uint8_t status;
uint8_t read_state;
uint8_t write_state;
uint8_t write_latch;
uint8_t rw_mode;
uint8_t mode;
uint8_t bcd; /* not supported */
uint8_t gate; /* timer start */
int64_t count_load_time;
/* irq handling */
int64_t next_transition_time;
QEMUTimer *irq_timer;
qemu_irq irq;
uint32_t irq_disabled;
} PITChannelState;
struct PITCommonState {
ISADevice dev;
MemoryRegion ioports;
uint32_t iobase;
PITChannelState channels[3];
};
struct PITCommonClass {
DeviceClass parent_class;
void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
PITChannelInfo *info);
void (*pre_save)(PITCommonState *s);
void (*post_load)(PITCommonState *s);
};
int pit_get_out(PITChannelState *s, int64_t current_time);
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);
void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
PITChannelInfo *info);
void pit_reset_common(PITCommonState *s);
#endif /* QEMU_I8254_INTERNAL_H */
include/hw/timer/ibex_timer.h
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/*
* QEMU lowRISC Ibex Timer device
*
* Copyright (c) 2021 Western Digital
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_IBEX_TIMER_H
#define HW_IBEX_TIMER_H
#include "hw/core/sysbus.h"
#define TYPE_IBEX_TIMER "ibex-timer"
OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
struct IbexTimerState {
/* <private> */
SysBusDevice parent_obj;
uint64_t mtimecmp;
QEMUTimer *mtimer; /* Internal timer for M-mode interrupt */
/* <public> */
MemoryRegion mmio;
uint32_t timer_ctrl;
uint32_t timer_cfg0;
uint32_t timer_compare_lower0;
uint32_t timer_compare_upper0;
uint32_t timer_intr_enable;
uint32_t timer_intr_state;
uint32_t timebase_freq;
qemu_irq irq;
qemu_irq m_timer_irq;
};
#endif /* HW_IBEX_TIMER_H */
include/hw/timer/imx_epit.h
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/*
* i.MX EPIT Timer
*
* Copyright (c) 2008 OK Labs
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
* Updated by Peter Chubb
* Updated by Jean-Christophe Dubois <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef IMX_EPIT_H
#define IMX_EPIT_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "hw/misc/imx_ccm.h"
#include "qom/object.h"
/*
* EPIT: Enhanced periodic interrupt timer
*/
#define CR_EN (1 << 0)
#define CR_ENMOD (1 << 1)
#define CR_OCIEN (1 << 2)
#define CR_RLD (1 << 3)
#define CR_PRESCALE_SHIFT (4)
#define CR_PRESCALE_BITS (12)
#define CR_SWR (1 << 16)
#define CR_IOVW (1 << 17)
#define CR_DBGEN (1 << 18)
#define CR_WAITEN (1 << 19)
#define CR_DOZEN (1 << 20)
#define CR_STOPEN (1 << 21)
#define CR_CLKSRC_SHIFT (24)
#define CR_CLKSRC_BITS (2)
#define SR_OCIF (1 << 0)
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
#define TYPE_IMX_EPIT "imx.epit"
OBJECT_DECLARE_SIMPLE_TYPE(IMXEPITState, IMX_EPIT)
struct IMXEPITState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
ptimer_state *timer_reload;
ptimer_state *timer_cmp;
MemoryRegion iomem;
IMXCCMState *ccm;
uint32_t cr;
uint32_t sr;
uint32_t lr;
uint32_t cmp;
qemu_irq irq;
};
#endif /* IMX_EPIT_H */
include/hw/timer/imx_gpt.h
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/*
* i.MX GPT Timer
*
* Copyright (c) 2008 OK Labs
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
* Updated by Peter Chubb
* Updated by Jean-Christophe Dubois <[email protected]>
* Updated by Gaurav Sharma <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef IMX_GPT_H
#define IMX_GPT_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "hw/misc/imx_ccm.h"
#include "qom/object.h"
/*
* GPT : General purpose timer
*
* This timer counts up continuously while it is enabled, resetting itself
* to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
* reaches the value of one of the ocrX (in periodic mode).
*/
#define GPT_TIMER_MAX 0XFFFFFFFFUL
/* Control register. Not all of these bits have any effect (yet) */
#define GPT_CR_EN (1 << 0) /* GPT Enable */
#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
#define GPT_CR_CLKSRC_SHIFT (6)
#define GPT_CR_CLKSRC_MASK (0x7)
#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
#define GPT_CR_SWR (1 << 15) /* Software Reset */
#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
#define GPT_SR_OF1 (1 << 0)
#define GPT_SR_OF2 (1 << 1)
#define GPT_SR_OF3 (1 << 2)
#define GPT_SR_ROV (1 << 5)
#define GPT_IR_OF1IE (1 << 0)
#define GPT_IR_OF2IE (1 << 1)
#define GPT_IR_OF3IE (1 << 2)
#define GPT_IR_ROVIE (1 << 5)
#define TYPE_IMX25_GPT "imx25.gpt"
#define TYPE_IMX31_GPT "imx31.gpt"
#define TYPE_IMX6_GPT "imx6.gpt"
#define TYPE_IMX6UL_GPT "imx6ul.gpt"
#define TYPE_IMX7_GPT "imx7.gpt"
#define TYPE_IMX8MP_GPT "imx8mp.gpt"
#define TYPE_IMX8MM_GPT "imx8mm.gpt"
#define TYPE_IMX_GPT TYPE_IMX25_GPT
typedef struct IMXGPTState IMXGPTState;
DECLARE_INSTANCE_CHECKER(IMXGPTState, IMX_GPT,
TYPE_IMX_GPT)
struct IMXGPTState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
ptimer_state *timer;
MemoryRegion iomem;
IMXCCMState *ccm;
uint32_t cr;
uint32_t pr;
uint32_t sr;
uint32_t ir;
uint32_t ocr1;
uint32_t ocr2;
uint32_t ocr3;
uint32_t icr1;
uint32_t icr2;
uint32_t cnt;
uint32_t next_timeout;
uint32_t next_int;
uint32_t freq;
qemu_irq irq;
const IMXClk *clocks;
};
#endif /* IMX_GPT_H */
include/hw/timer/mips_gictimer.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2016 Imagination Technologies
*
*/
#ifndef MIPS_GICTIMER_H
#define MIPS_GICTIMER_H
typedef struct MIPSGICTimerVPState MIPSGICTimerVPState;
typedef struct MIPSGICTimerState MIPSGICTimerState;
typedef void MIPSGICTimerCB(void *opaque, uint32_t vp_index);
struct MIPSGICTimerVPState {
QEMUTimer *qtimer;
uint32_t vp_index;
uint32_t comparelo;
MIPSGICTimerState *gictimer;
};
struct MIPSGICTimerState {
void *opaque;
uint8_t countstop;
uint32_t sh_counterlo;
int32_t num_vps;
MIPSGICTimerVPState *vptimers;
MIPSGICTimerCB *cb;
};
uint32_t mips_gictimer_get_freq(MIPSGICTimerState *gic);
uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
uint32_t vp_index);
void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
uint64_t compare);
uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
void mips_gictimer_start_count(MIPSGICTimerState *gic);
void mips_gictimer_stop_count(MIPSGICTimerState *gic);
MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
MIPSGICTimerCB *cb);
#endif /* MIPS_GICTIMER_H */
include/hw/timer/mss-timer.h
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/*
* Microsemi SmartFusion2 Timer.
*
* Copyright (c) 2017 Subbaraya Sundeep <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_MSS_TIMER_H
#define HW_MSS_TIMER_H
#include "hw/core/sysbus.h"
#include "hw/core/ptimer.h"
#include "qom/object.h"
#define TYPE_MSS_TIMER "mss-timer"
OBJECT_DECLARE_SIMPLE_TYPE(MSSTimerState, MSS_TIMER)
/*
* There are two 32-bit down counting timers.
* Timers 1 and 2 can be concatenated into a single 64-bit Timer
* that operates either in Periodic mode or in One-shot mode.
* Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
* In 64-bit mode, writing to the 32-bit registers has no effect.
* Similarly, in 32-bit mode, writing to the 64-bit mode registers
* has no effect. Only two 32-bit timers are supported currently.
*/
#define NUM_TIMERS 2
#define R_TIM1_MAX 6
struct Msf2Timer {
ptimer_state *ptimer;
uint32_t regs[R_TIM1_MAX];
qemu_irq irq;
};
struct MSSTimerState {
SysBusDevice parent_obj;
MemoryRegion mmio;
uint32_t freq_hz;
struct Msf2Timer timers[NUM_TIMERS];
};
#endif /* HW_MSS_TIMER_H */
include/hw/timer/npcm7xx_timer.h
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/*
* Nuvoton NPCM7xx Timer Controller
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef NPCM7XX_TIMER_H
#define NPCM7XX_TIMER_H
#include "system/memory.h"
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
#define NPCM7XX_TIMERS_PER_CTRL (5)
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
/* The basic watchdog timer period is 2^14 clock cycles. */
#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
/**
* struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
* watchdog timer use.
* @qtimer: QEMU timer that notifies us on expiration.
* @expires_ns: Absolute virtual expiration time.
* @remaining_ns: Remaining time until expiration if timer is paused.
*/
typedef struct NPCM7xxBaseTimer {
QEMUTimer qtimer;
int64_t expires_ns;
int64_t remaining_ns;
} NPCM7xxBaseTimer;
/**
* struct NPCM7xxTimer - Individual timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @base_timer: The basic timer functionality for this timer.
* @tcsr: The Timer Control and Status Register.
* @ticr: The Timer Initial Count Register.
*/
typedef struct NPCM7xxTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
NPCM7xxBaseTimer base_timer;
uint32_t tcsr;
uint32_t ticr;
} NPCM7xxTimer;
/**
* struct NPCM7xxWatchdogTimer - The watchdog timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @reset_signal: The GPIO used to send a reset signal.
* @base_timer: The basic timer functionality for this timer.
* @wtcr: The Watchdog Timer Control Register.
*/
typedef struct NPCM7xxWatchdogTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
qemu_irq reset_signal;
NPCM7xxBaseTimer base_timer;
uint32_t wtcr;
} NPCM7xxWatchdogTimer;
/**
* struct NPCM7xxTimerCtrlState - Timer Module device state.
* @parent: System bus device.
* @iomem: Memory region through which registers are accessed.
* @index: The index of this timer module.
* @tisr: The Timer Interrupt Status Register.
* @timer: The five individual timers managed by this module.
* @watchdog_timer: The watchdog timer managed by this module.
*/
struct NPCM7xxTimerCtrlState {
SysBusDevice parent;
MemoryRegion iomem;
uint32_t tisr;
Clock *clock;
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
NPCM7xxWatchdogTimer watchdog_timer;
};
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
#define NPCM7XX_TIMER(obj) \
OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
#endif /* NPCM7XX_TIMER_H */
include/hw/timer/nrf51_timer.h
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/*
* nRF51 System-on-Chip Timer peripheral
*
* QEMU interface:
* + sysbus MMIO regions 0: GPIO registers
* + sysbus irq
*
* Copyright 2018 Steffen Görtz <[email protected]>
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
#ifndef NRF51_TIMER_H
#define NRF51_TIMER_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
#define TYPE_NRF51_TIMER "nrf51_soc.timer"
OBJECT_DECLARE_SIMPLE_TYPE(NRF51TimerState, NRF51_TIMER)
#define NRF51_TIMER_REG_COUNT 4
#define NRF51_TIMER_TASK_START 0x000
#define NRF51_TIMER_TASK_STOP 0x004
#define NRF51_TIMER_TASK_COUNT 0x008
#define NRF51_TIMER_TASK_CLEAR 0x00C
#define NRF51_TIMER_TASK_SHUTDOWN 0x010
#define NRF51_TIMER_TASK_CAPTURE_0 0x040
#define NRF51_TIMER_TASK_CAPTURE_3 0x04C
#define NRF51_TIMER_EVENT_COMPARE_0 0x140
#define NRF51_TIMER_EVENT_COMPARE_1 0x144
#define NRF51_TIMER_EVENT_COMPARE_2 0x148
#define NRF51_TIMER_EVENT_COMPARE_3 0x14C
#define NRF51_TIMER_REG_SHORTS 0x200
#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f
#define NRF51_TIMER_REG_INTENSET 0x304
#define NRF51_TIMER_REG_INTENCLR 0x308
#define NRF51_TIMER_REG_INTEN_MASK 0xf0000
#define NRF51_TIMER_REG_MODE 0x504
#define NRF51_TIMER_REG_MODE_MASK 0x01
#define NRF51_TIMER_TIMER 0
#define NRF51_TIMER_COUNTER 1
#define NRF51_TIMER_REG_BITMODE 0x508
#define NRF51_TIMER_REG_BITMODE_MASK 0x03
#define NRF51_TIMER_WIDTH_16 0
#define NRF51_TIMER_WIDTH_8 1
#define NRF51_TIMER_WIDTH_24 2
#define NRF51_TIMER_WIDTH_32 3
#define NRF51_TIMER_REG_PRESCALER 0x510
#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F
#define NRF51_TIMER_REG_CC0 0x540
#define NRF51_TIMER_REG_CC3 0x54C
struct NRF51TimerState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
uint8_t id;
QEMUTimer timer;
int64_t timer_start_ns;
int64_t update_counter_ns;
uint32_t counter;
bool running;
uint8_t events_compare[NRF51_TIMER_REG_COUNT];
uint32_t cc[NRF51_TIMER_REG_COUNT];
uint32_t shorts;
uint32_t inten;
uint32_t mode;
uint32_t bitmode;
uint32_t prescaler;
};
#endif
include/hw/timer/qct-qtimer.h
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/*
* Qualcomm QCT QTimer
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_TIMER_QCT_QTIMER_H
#define HW_TIMER_QCT_QTIMER_H
#include "qom/object.h"
#define TYPE_QCT_QTIMER "qct-qtimer"
/* QTimer interface for external access from hexagon_globalreg */
#define TYPE_QCT_QTIMER_INTERFACE "qct-qtimer-if"
typedef struct QctQtimerInterface QctQtimerInterface;
typedef struct QctQtimerInterfaceClass {
InterfaceClass parent_class;
/* Read the live physical counter, backing HEX_SREG_TIMERLO/TIMERHI */
uint32_t (*get_timer_lo)(const QctQtimerInterface *qtimer);
uint32_t (*get_timer_hi)(const QctQtimerInterface *qtimer);
} QctQtimerInterfaceClass;
DECLARE_OBJ_CHECKERS(QctQtimerInterface, QctQtimerInterfaceClass,
QCT_QTIMER_INTERFACE, TYPE_QCT_QTIMER_INTERFACE);
static inline uint32_t qct_qtimer_get_timer_lo(const QctQtimerInterface *qtimer)
{
QctQtimerInterfaceClass *k = QCT_QTIMER_INTERFACE_GET_CLASS(qtimer);
return k->get_timer_lo(qtimer);
}
static inline uint32_t qct_qtimer_get_timer_hi(const QctQtimerInterface *qtimer)
{
QctQtimerInterfaceClass *k = QCT_QTIMER_INTERFACE_GET_CLASS(qtimer);
return k->get_timer_hi(qtimer);
}
#endif /* HW_TIMER_QCT_QTIMER_H */
include/hw/timer/renesas_cmt.h
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/*
* Renesas Compare-match timer Object
*
* Copyright (c) 2019 Yoshinori Sato
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_TIMER_RENESAS_CMT_H
#define HW_TIMER_RENESAS_CMT_H
#include "qemu/timer.h"
#include "hw/core/sysbus.h"
#include "qom/object.h"
#define TYPE_RENESAS_CMT "renesas-cmt"
typedef struct RCMTState RCMTState;
DECLARE_INSTANCE_CHECKER(RCMTState, RCMT,
TYPE_RENESAS_CMT)
enum {
CMT_CH = 2,
CMT_NR_IRQ = 1 * CMT_CH
};
struct RCMTState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint64_t input_freq;
MemoryRegion memory;
uint16_t cmstr;
uint16_t cmcr[CMT_CH];
uint16_t cmcnt[CMT_CH];
uint16_t cmcor[CMT_CH];
int64_t tick[CMT_CH];
qemu_irq cmi[CMT_CH];
QEMUTimer timer[CMT_CH];
};
#endif
include/hw/timer/renesas_tmr.h
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/*
* Renesas 8bit timer Object
*
* Copyright (c) 2018 Yoshinori Sato
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_TIMER_RENESAS_TMR_H
#define HW_TIMER_RENESAS_TMR_H
#include "qemu/timer.h"
#include "hw/core/sysbus.h"
#include "qom/object.h"
#define TYPE_RENESAS_TMR "renesas-tmr"
typedef struct RTMRState RTMRState;
DECLARE_INSTANCE_CHECKER(RTMRState, RTMR,
TYPE_RENESAS_TMR)
enum timer_event {
cmia = 0,
cmib = 1,
ovi = 2,
none = 3,
TMR_NR_EVENTS = 4
};
enum {
TMR_CH = 2,
TMR_NR_IRQ = 3 * TMR_CH
};
struct RTMRState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint64_t input_freq;
MemoryRegion memory;
int64_t tick;
uint8_t tcnt[TMR_CH];
uint8_t tcora[TMR_CH];
uint8_t tcorb[TMR_CH];
uint8_t tcr[TMR_CH];
uint8_t tccr[TMR_CH];
uint8_t tcor[TMR_CH];
uint8_t tcsr[TMR_CH];
int64_t div_round[TMR_CH];
uint8_t next[TMR_CH];
qemu_irq cmia[TMR_CH];
qemu_irq cmib[TMR_CH];
qemu_irq ovi[TMR_CH];
QEMUTimer timer[TMR_CH];
};
#endif
include/hw/timer/sifive_pwm.h
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/*
* SiFive PWM
*
* Copyright (c) 2020 Western Digital
*
* Author: Alistair Francis <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_SIFIVE_PWM_H
#define HW_SIFIVE_PWM_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
#define TYPE_SIFIVE_PWM "sifive-pwm"
#define SIFIVE_PWM(obj) \
OBJECT_CHECK(SiFivePwmState, (obj), TYPE_SIFIVE_PWM)
#define SIFIVE_PWM_CHANS 4
#define SIFIVE_PWM_IRQS SIFIVE_PWM_CHANS
typedef struct SiFivePwmState {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion mmio;
QEMUTimer timer[SIFIVE_PWM_CHANS];
/*
* if en bit(s) set, is the number of ticks when pwmcount was 0
* if en bit(s) not set, is the number of ticks in pwmcount
*/
uint64_t tick_offset;
uint64_t freq_hz;
uint32_t pwmcfg;
uint32_t pwmcmp[SIFIVE_PWM_CHANS];
qemu_irq irqs[SIFIVE_PWM_IRQS];
} SiFivePwmState;
#endif /* HW_SIFIVE_PWM_H */
include/hw/timer/sse-counter.h
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/*
* Arm SSE Subsystem System Counter
*
* Copyright (c) 2020 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "System counter" which is documented in
* the Arm SSE-123 Example Subsystem Technical Reference Manual:
* https://developer.arm.com/documentation/101370/latest/
*
* QEMU interface:
* + Clock input "CLK": clock
* + sysbus MMIO region 0: the control register frame
* + sysbus MMIO region 1: the status register frame
*
* Consumers of the system counter's timestamp, such as the SSE
* System Timer device, can also use the APIs sse_counter_for_timestamp(),
* sse_counter_tick_to_time() and sse_counter_register_consumer() to
* interact with an instance of the System Counter. Generally the
* consumer device should have a QOM link property which the board
* code can set to the appropriate instance of the system counter.
*/
#ifndef SSE_COUNTER_H
#define SSE_COUNTER_H
#include "hw/core/sysbus.h"
#include "qom/object.h"
#include "qemu/notify.h"
#define TYPE_SSE_COUNTER "sse-counter"
OBJECT_DECLARE_SIMPLE_TYPE(SSECounter, SSE_COUNTER)
struct SSECounter {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion control_mr;
MemoryRegion status_mr;
Clock *clk;
NotifierList notifier_list;
uint32_t cntcr;
uint32_t cntscr0;
/*
* These are used for handling clock frequency changes: they are a
* tuple of (QEMU_CLOCK_VIRTUAL timestamp, CNTCV at that time),
* taken when the clock frequency changes. sse_cntcv() needs them
* to calculate the current CNTCV.
*/
uint64_t ns_then;
uint64_t ticks_then;
};
/*
* These functions are the interface by which a consumer of
* the system timestamp (such as the SSE system timer device)
* can communicate with the SSECounter.
*/
/**
* sse_counter_for_timestamp:
* @counter: SSECounter
* @ns: timestamp of QEMU_CLOCK_VIRTUAL in nanoseconds
*
* Returns the value of the timestamp counter at the specified
* point in time (assuming that no changes to scale factor, enable, etc
* happen in the meantime).
*/
uint64_t sse_counter_for_timestamp(SSECounter *counter, uint64_t ns);
/**
* sse_counter_tick_to_time:
* @counter: SSECounter
* @tick: tick value
*
* Returns the time (a QEMU_CLOCK_VIRTUAL timestamp in nanoseconds)
* when the timestamp counter will reach the specified tick count.
* If the counter is not currently running, returns UINT64_MAX.
*/
uint64_t sse_counter_tick_to_time(SSECounter *counter, uint64_t tick);
/**
* sse_counter_register_consumer:
* @counter: SSECounter
* @notifier: Notifier which is notified on counter changes
*
* Registers @notifier with the SSECounter. When the counter's
* configuration changes in a way that might invalidate information
* previously returned via sse_counter_for_timestamp() or
* sse_counter_tick_to_time(), the notifier will be called.
* Devices which consume the timestamp counter can use this as
* a cue to recalculate timer events.
*/
void sse_counter_register_consumer(SSECounter *counter, Notifier *notifier);
#endif
include/hw/timer/sse-timer.h
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/*
* Arm SSE Subsystem System Timer
*
* Copyright (c) 2020 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "System timer" which is documented in
* the Arm SSE-123 Example Subsystem Technical Reference Manual:
* https://developer.arm.com/documentation/101370/latest/
*
* QEMU interface:
* + QOM property "counter": link property to be set to the
* TYPE_SSE_COUNTER timestamp counter device this timer runs off
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: timer interrupt
*/
#ifndef SSE_TIMER_H
#define SSE_TIMER_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
#include "hw/timer/sse-counter.h"
#define TYPE_SSE_TIMER "sse-timer"
OBJECT_DECLARE_SIMPLE_TYPE(SSETimer, SSE_TIMER)
struct SSETimer {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
SSECounter *counter;
QEMUTimer timer;
Notifier counter_notifier;
uint32_t cntfrq;
uint32_t cntp_ctl;
uint64_t cntp_cval;
uint64_t cntp_aival;
uint32_t cntp_aival_ctl;
uint32_t cntp_aival_reload;
};
#endif
include/hw/timer/stellaris-gptm.h
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/*
* Luminary Micro Stellaris General Purpose Timer Module
*
* Copyright (c) 2006 CodeSourcery.
* Written by Paul Brook
*
* This code is licensed under the GPL.
*/
#ifndef HW_TIMER_STELLARIS_GPTM_H
#define HW_TIMER_STELLARIS_GPTM_H
#include "qom/object.h"
#include "hw/core/sysbus.h"
#include "hw/core/irq.h"
#include "hw/core/clock.h"
#define TYPE_STELLARIS_GPTM "stellaris-gptm"
OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
/*
* QEMU interface:
* + sysbus MMIO region 0: register bank
* + sysbus IRQ 0: timer interrupt
* + unnamed GPIO output 0: trigger output for the ADC
* + Clock input "clk": the 32-bit countdown timer runs at this speed
*/
struct gptm_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t config;
uint32_t mode[2];
uint32_t control;
uint32_t state;
uint32_t mask;
uint32_t load[2];
uint32_t match[2];
uint32_t prescale[2];
uint32_t match_prescale[2];
uint32_t rtc;
int64_t tick[2];
struct gptm_state *opaque[2];
QEMUTimer *timer[2];
/* The timers have an alternate output used to trigger the ADC. */
qemu_irq trigger;
qemu_irq irq;
Clock *clk;
};
#endif
include/hw/timer/stm32f2xx_timer.h
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/*
* STM32F2XX Timer
*
* Copyright (c) 2014 Alistair Francis <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_STM32F2XX_TIMER_H
#define HW_STM32F2XX_TIMER_H
#include "hw/core/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
#define TIM_CR1 0x00
#define TIM_CR2 0x04
#define TIM_SMCR 0x08
#define TIM_DIER 0x0C
#define TIM_SR 0x10
#define TIM_EGR 0x14
#define TIM_CCMR1 0x18
#define TIM_CCMR2 0x1C
#define TIM_CCER 0x20
#define TIM_CNT 0x24
#define TIM_PSC 0x28
#define TIM_ARR 0x2C
#define TIM_CCR1 0x34
#define TIM_CCR2 0x38
#define TIM_CCR3 0x3C
#define TIM_CCR4 0x40
#define TIM_DCR 0x48
#define TIM_DMAR 0x4C
#define TIM_OR 0x50
#define TIM_CR1_CEN 1
#define TIM_EGR_UG 1
#define TIM_CCER_CC2E (1 << 4)
#define TIM_CCMR1_OC2M2 (1 << 14)
#define TIM_CCMR1_OC2M1 (1 << 13)
#define TIM_CCMR1_OC2M0 (1 << 12)
#define TIM_CCMR1_OC2PE (1 << 11)
#define TIM_DIER_UIE 1
#define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
typedef struct STM32F2XXTimerState STM32F2XXTimerState;
DECLARE_INSTANCE_CHECKER(STM32F2XXTimerState, STM32F2XXTIMER,
TYPE_STM32F2XX_TIMER)
struct STM32F2XXTimerState {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion iomem;
QEMUTimer *timer;
qemu_irq irq;
int64_t tick_offset;
uint64_t hit_time;
uint64_t freq_hz;
uint32_t tim_cr1;
uint32_t tim_cr2;
uint32_t tim_smcr;
uint32_t tim_dier;
uint32_t tim_sr;
uint32_t tim_egr;
uint32_t tim_ccmr1;
uint32_t tim_ccmr2;
uint32_t tim_ccer;
uint32_t tim_psc;
uint32_t tim_arr;
uint32_t tim_ccr1;
uint32_t tim_ccr2;
uint32_t tim_ccr3;
uint32_t tim_ccr4;
uint32_t tim_dcr;
uint32_t tim_dmar;
uint32_t tim_or;
};
#endif /* HW_STM32F2XX_TIMER_H */
include/hw/timer/tmu012.h
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/*
* SuperH Timer
*
* Copyright (c) 2007 Magnus Damm
*
* This code is licensed under the GPL.
*/
#ifndef HW_TIMER_TMU012_H
#define HW_TIMER_TMU012_H
#include "exec/hwaddr.h"
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
void tmu012_init(MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
#endif