Import QEMU upstream snapshot d2e570c
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
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/*
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* host-signal.h: signal info dependent on the host architecture
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2021 Linaro Limited
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef AARCH64_HOST_SIGNAL_H
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#define AARCH64_HOST_SIGNAL_H
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/* The third argument to a SA_SIGINFO handler is ucontext_t. */
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typedef ucontext_t host_sigcontext;
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/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
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#ifndef ESR_MAGIC
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#define ESR_MAGIC 0x45535201
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struct esr_context {
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struct _aarch64_ctx head;
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uint64_t esr;
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};
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#endif
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static inline struct _aarch64_ctx *first_ctx(host_sigcontext *uc)
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{
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return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
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}
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static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
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{
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return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
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}
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static inline uintptr_t host_signal_pc(host_sigcontext *uc)
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{
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return uc->uc_mcontext.pc;
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}
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static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
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{
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uc->uc_mcontext.pc = pc;
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}
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static inline void *host_signal_mask(host_sigcontext *uc)
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{
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return &uc->uc_sigmask;
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}
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static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
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{
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struct _aarch64_ctx *hdr;
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uint32_t insn;
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/* Find the esr_context, which has the WnR bit in it */
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for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
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if (hdr->magic == ESR_MAGIC) {
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struct esr_context const *ec = (struct esr_context const *)hdr;
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uint64_t esr = ec->esr;
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/* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
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return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
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}
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}
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/*
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* Fall back to parsing instructions; will only be needed
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* for really ancient (pre-3.16) kernels.
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*/
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insn = *(uint32_t *)host_signal_pc(uc);
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return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
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|| (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
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|| (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
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|| (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
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|| (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
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|| (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
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|| (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
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/* Ignore bits 10, 11 & 21, controlling indexing. */
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|| (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
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|| (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
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/* Ignore bits 23 & 24, controlling indexing. */
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|| (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */
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}
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#endif
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