Import QEMU upstream snapshot d2e570c
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
This commit is contained in:
Binary file not shown.
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/*
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* Device Tree Source for AMCC Bamboo
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*
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* Copyright (c) 2006, 2007 IBM Corp.
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* Josh Boyer <[email protected]>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "amcc,bamboo";
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compatible = "amcc,bamboo";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,440EP";
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reg = <0>;
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clock-frequency = <0x1fca0550>;
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timebase-frequency = <0x017d7840>;
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i-cache-line-size = <0x20>;
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d-cache-line-size = <0x20>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x9000000>;
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-440ep","ibm,uic";
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interrupt-controller;
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cell-index = <0x0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0x0>;
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#size-cells = <0x0>;
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#interrupt-cells = <0x2>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-440ep";
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dcr-reg = <0x00e 0x002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-440ep";
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dcr-reg = <0x00c 0x002>;
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};
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plb {
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compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0x07f28154>;
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SDRAM0: sdram {
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compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
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dcr-reg = <0x010 0x2>;
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};
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DMA0: dma {
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compatible = "ibm,dma-440ep", "ibm,dma-440gp";
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dcr-reg = <0x100 0x027>;
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};
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POB0: opb {
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compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Bamboo is oddball in the 44x world and doesn't use the ERPN
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* bits.
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*/
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ranges = <0x00000000 0x0 0x00000000 0x80000000
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0x80000000 0x0 0x80000000 0x80000000>;
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/* interrupt-parent = <&UIC1>; */
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interrupts = <7 4>;
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clock-frequency = <0x03f940aa>;
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EBC0: ebc {
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compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
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dcr-reg = <0x012 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0x03f940aa>;
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interrupts = <5 1>;
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/* interrupt-parent = <&UIC1>; */
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};
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 8>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0x00a8c000>;
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current-speed = <0x1c200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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UART1: serial@ef600400 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600400 8>;
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virtual-reg = <0xef600400>;
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clock-frequency = <0x00a8c000>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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IIC0: i2c@ef600700 {
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device_type = "i2c";
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compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
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reg = <0xef600700 0x14>;
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interrupt-parent = <&UIC0>;
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interrupts = <2 4>;
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};
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IIC1: i2c@ef600800 {
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device_type = "i2c";
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compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
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reg = <0xef600800 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <7 4>;
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};
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ZMII0: emac-zmii@ef600d00 {
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device_type = "zmii-interface";
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compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
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reg = <0xef600d00 0xc>;
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};
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};
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PCI0: pci@ec000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
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primary;
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reg = <0 0xeec00000 8 /* Config space access */
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0 0xeed00000 4 /* IACK */
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0 0xeed00000 4 /* Special cycle */
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0 0xef400000 0x40>; /* Internal registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed. Chip supports a second
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* IO range but we don't use it for now
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*/
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ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
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0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>;
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/* Bamboo has all 4 IRQ pins tied together per slot */
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interrupt-map-mask = <0xf800 0 0 0>;
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interrupt-map = <
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/* IDSEL 1 */
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0x0800 0 0 0 &UIC0 0x1c 8
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/* IDSEL 2 */
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0x1000 0 0 0 &UIC0 0x1b 8
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/* IDSEL 3 */
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0x1800 0 0 0 &UIC0 0x1a 8
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/* IDSEL 4 */
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0x2000 0 0 0 &UIC0 0x19 8
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>;
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};
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@ef600300";
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};
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};
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Binary file not shown.
@@ -0,0 +1,566 @@
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/*
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* Device Tree Source for AMCC Canyonlands (460EX)
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*
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* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <[email protected]>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "amcc,canyonlands";
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compatible = "amcc,canyonlands";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC0;
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ethernet1 = &EMAC1;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,460EX";
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reg = <0x00000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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next-level-cache = <&L2C0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0x0e0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC3: interrupt-controller3 {
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compatible = "ibm,uic-460ex","ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0x0f0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-460ex";
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dcr-reg = <0x00e 0x002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-460ex";
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dcr-reg = <0x00c 0x002>;
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};
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CPM0: cpm {
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compatible = "ibm,cpm";
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dcr-access-method = "native";
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dcr-reg = <0x160 0x003>;
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unused-units = <0x00000100>;
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idle-doze = <0x02000000>;
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standby = <0xfeff791d>;
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};
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L2C0: l2c {
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compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
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dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
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0x030 0x008>; /* L2 cache DCR's */
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cache-line-size = <32>; /* 32 bytes */
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cache-size = <262144>; /* L2, 256K */
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interrupt-parent = <&UIC1>;
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interrupts = <11 1>;
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};
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plb {
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compatible = "ibm,plb-460ex", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: sdram {
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compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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CRYPTO: crypto@180000 {
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compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
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reg = <4 0x00180000 0x80400>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1d 0x4>;
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};
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HWRNG: hwrng@110000 {
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compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
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reg = <4 0x00110000 0x50>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <2>;
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||||
num-rx-chans = <16>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-parent = <&UIC2>;
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||||
interrupts = < /*TXEOB*/ 0x6 0x4
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||||
/*RXEOB*/ 0x7 0x4
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||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
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/*RXDE*/ 0x5 0x4>;
|
||||
};
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||||
|
||||
USB0: ehci@bffd0400 {
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||||
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
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||||
interrupt-parent = <&UIC2>;
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||||
interrupts = <0x1d 4>;
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||||
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
|
||||
};
|
||||
|
||||
USB1: usb@bffd0000 {
|
||||
compatible = "ohci-le";
|
||||
reg = <4 0xbffd0000 0x60>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1e 4>;
|
||||
};
|
||||
|
||||
USBOTG0: usbotg@bff80000 {
|
||||
compatible = "amcc,dwc-otg";
|
||||
reg = <0x4 0xbff80000 0x10000>;
|
||||
interrupt-parent = <&USBOTG0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0x0 0x1 0x2>;
|
||||
interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
|
||||
/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
|
||||
/* DMA */ 0x2 &UIC0 0xc 0x4>;
|
||||
};
|
||||
|
||||
AHBDMA: dma@bffd0800 {
|
||||
compatible = "snps,dma-spear1340";
|
||||
reg = <4 0xbffd0800 0x400>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x5 0x4>;
|
||||
#dma-cells = <3>;
|
||||
};
|
||||
|
||||
SATA0: sata@bffd1000 {
|
||||
compatible = "amcc,sata-460ex";
|
||||
reg = <4 0xbffd1000 0x800>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x0 0x4>;
|
||||
dmas = <&AHBDMA 0 1 0>;
|
||||
dma-names = "sata-dma";
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460ex", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "amcc,ppc460ex-bcsr";
|
||||
reg = <2 0x0 0x9>;
|
||||
};
|
||||
|
||||
ndfc@3,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "user";
|
||||
reg = <0x00000000 0x03f00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "st,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x19 0x8>;
|
||||
};
|
||||
sttm@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x14 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600b00 {
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600b00 0x00000048>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460ex", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00000000>;
|
||||
msi-mask = <0x44440000>;
|
||||
interrupt-count = <3>;
|
||||
interrupts = <0 1 2 3>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
dtbs = [
|
||||
'bamboo.dtb',
|
||||
'canyonlands.dtb',
|
||||
'pegasos1.dtb',
|
||||
'pegasos2.dtb',
|
||||
'petalogix-ml605.dtb',
|
||||
'petalogix-s3adsp1800.dtb',
|
||||
]
|
||||
|
||||
dtc = find_program('dtc', required: false)
|
||||
if dtc.found()
|
||||
foreach out : dtbs
|
||||
f = fs.replace_suffix(out, '.dts')
|
||||
custom_target(out,
|
||||
build_by_default: have_system,
|
||||
input: files(f),
|
||||
output: out,
|
||||
install: get_option('install_blobs'),
|
||||
install_dir: qemu_datadir / 'dtb',
|
||||
command: [ dtc, '-q', '-I', 'dts', '-O', 'dtb',
|
||||
'-o', '@OUTPUT@', '@INPUT0@' ])
|
||||
endforeach
|
||||
else
|
||||
install_data(dtbs, install_dir: qemu_datadir / 'dtb')
|
||||
endif
|
||||
Binary file not shown.
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* QEMU Pegasos1 Device Tree Source
|
||||
*
|
||||
* Copyright 2025 BALATON Zoltan
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* This is partial source, more info will be filled in by board code.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
device_type = "chrp";
|
||||
model = "Pegasos";
|
||||
revision = "1A";
|
||||
CODEGEN,vendor = "bplan GmbH";
|
||||
CODEGEN,board = "Pegasos";
|
||||
CODEGEN,description = "Pegasos CHRP PowerPC System";
|
||||
|
||||
openprom {
|
||||
model = "Pegasos,0.1b123";
|
||||
};
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#cpus = <1>;
|
||||
};
|
||||
|
||||
failsafe {
|
||||
device_type = "serial";
|
||||
};
|
||||
|
||||
pci@80000000 {
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
clock-frequency = <33333333>;
|
||||
8259-interrupt-acknowledge = <0xfef00000>;
|
||||
reg = <0x80000000 0x7f000000>;
|
||||
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00800000
|
||||
0x02000000 0 0x80000000 0x80000000 0 0x7d000000
|
||||
0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>;
|
||||
bus-range = <0 0>;
|
||||
|
||||
isa@7 {
|
||||
vendor-id = <0x1106>;
|
||||
device-id = <0x8231>;
|
||||
revision-id = <0x10>;
|
||||
class-code = <0x60100>;
|
||||
/* Pegasos firmware has subsystem-id and */
|
||||
/* subsystem-vendor-id swapped */
|
||||
subsystem-id = <0x1af4>;
|
||||
subsystem-vendor-id = <0x1100>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
device_type = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
eisa-slots = <0>;
|
||||
clock-frequency = <8333333>;
|
||||
slot-names = <0>;
|
||||
|
||||
serial@i2f8 {
|
||||
device_type = "serial";
|
||||
reg = <1 0x2f8 8>;
|
||||
interrupts = <3 0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
8042@i60 {
|
||||
device_type = "";
|
||||
reg = <1 0x60 5>;
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller = "";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
keyboard@i60 {
|
||||
device_type = "keyboard";
|
||||
reg = <1 0x60 5>;
|
||||
interrupts = <1 0>;
|
||||
};
|
||||
|
||||
rtc@i70 {
|
||||
device_type = "rtc";
|
||||
reg = <1 0x70 2>;
|
||||
interrupts = <8 0>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "ds1385-rtc";
|
||||
};
|
||||
|
||||
timer@i40 {
|
||||
device_type = "timer";
|
||||
reg = <1 0x40 8>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
fdc@i3f0 {
|
||||
device_type = "fdc";
|
||||
reg = <1 0x3f0 8>;
|
||||
interrupts = <6 0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
lpt@i3bc {
|
||||
device_type = "lpt";
|
||||
reg = <1 0x3bc 8>;
|
||||
interrupts = <7 0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Binary file not shown.
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* QEMU Pegasos2 Device Tree Source
|
||||
*
|
||||
* Copyright 2025 BALATON Zoltan
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* This is partial source, more info will be filled in by board code.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
device_type = "chrp";
|
||||
model = "Pegasos2";
|
||||
revision = "2B";
|
||||
CODEGEN,vendor = "bplan GmbH";
|
||||
CODEGEN,board = "Pegasos2";
|
||||
CODEGEN,description = "Pegasos CHRP PowerPC System";
|
||||
|
||||
openprom {
|
||||
model = "Pegasos2,1.1";
|
||||
};
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#cpus = <1>;
|
||||
};
|
||||
|
||||
rtas {
|
||||
rtas-version = <1>;
|
||||
rtas-size = <20>;
|
||||
rtas-display-device = <0>;
|
||||
rtas-event-scan-rate = <0>;
|
||||
rtas-error-log-max = <0>;
|
||||
restart-rtas = <0>;
|
||||
nvram-fetch = <1>;
|
||||
nvram-store = <2>;
|
||||
get-time-of-day = <3>;
|
||||
set-time-of-day = <4>;
|
||||
event-scan = <6>;
|
||||
/* Pegasos2 firmware misspells check-exception */
|
||||
check-execption = <7>;
|
||||
read-pci-config = <8>;
|
||||
write-pci-config = <9>;
|
||||
display-character = <10>;
|
||||
set-indicator = <11>;
|
||||
power-off = <17>;
|
||||
suspend = <18>;
|
||||
hibernate = <19>;
|
||||
system-reboot = <20>;
|
||||
};
|
||||
|
||||
failsafe {
|
||||
device_type = "serial";
|
||||
};
|
||||
|
||||
pci@80000000 {
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
clock-frequency = <33333333>;
|
||||
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00010000
|
||||
0x02000000 0 0x80000000 0x80000000 0 0x40000000>;
|
||||
8259-interrupt-acknowledge = <0xf1000cb4>;
|
||||
reg = <0x80000000 0x40000000>;
|
||||
pci-bridge-number = <0>;
|
||||
bus-range = <0 0>;
|
||||
|
||||
isa@c {
|
||||
vendor-id = <0x1106>;
|
||||
device-id = <0x8231>;
|
||||
revision-id = <0x10>;
|
||||
class-code = <0x60100>;
|
||||
/* Pegasos firmware has subsystem-id and
|
||||
subsystem-vendor-id swapped */
|
||||
subsystem-id = <0x1af4>;
|
||||
subsystem-vendor-id = <0x1100>;
|
||||
reg = <0x6000 0 0 0 0>;
|
||||
device_type = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
eisa-slots = <0>;
|
||||
clock-frequency = <8333333>;
|
||||
slot-names = <0>;
|
||||
|
||||
serial@i2f8 {
|
||||
device_type = "serial";
|
||||
reg = <1 0x2f8 8>;
|
||||
interrupts = <3 0>;
|
||||
clock-frequency = <1843200>;
|
||||
compatible = "pnpPNP,501";
|
||||
};
|
||||
|
||||
8042@i60 {
|
||||
device_type = "";
|
||||
reg = <1 0x60 5>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "chrp,8042";
|
||||
interrupt-controller = "";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
keyboard@i60 {
|
||||
device_type = "keyboard";
|
||||
reg = <1 0x60 5>;
|
||||
interrupts = <1 0>;
|
||||
compatible = "pnpPNP,303";
|
||||
};
|
||||
|
||||
rtc@i70 {
|
||||
device_type = "rtc";
|
||||
reg = <1 0x70 2>;
|
||||
interrupts = <8 0>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "ds1385-rtc";
|
||||
};
|
||||
|
||||
timer@i40 {
|
||||
device_type = "timer";
|
||||
reg = <1 0x40 8>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "pnpPNP,100";
|
||||
};
|
||||
|
||||
fdc@i3f0 {
|
||||
device_type = "fdc";
|
||||
reg = <1 0x3f0 8>;
|
||||
interrupts = <6 0>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "pnpPNP,700";
|
||||
};
|
||||
|
||||
lpt@i3bc {
|
||||
device_type = "lpt";
|
||||
reg = <1 0x3bc 8>;
|
||||
interrupts = <7 0>;
|
||||
clock-frequency = <0>;
|
||||
compatible = "pnpPNP,400";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci@c0000000 {
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
clock-frequency = <66666666>;
|
||||
ranges = <0x01000000 0 0x00000000 0xf8000000 0 0x00010000
|
||||
0x02000000 0 0xc0000000 0xc0000000 0 0x20000000>;
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
pci-bridge-number = <1>;
|
||||
bus-range = <0 0>;
|
||||
};
|
||||
};
|
||||
Binary file not shown.
@@ -0,0 +1,350 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Xilinx Inc.
|
||||
* Written by Edgar E. Iglesias <[email protected]>.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = < 0x01 >;
|
||||
#size-cells = < 0x01 >;
|
||||
compatible = "xlnx,microblaze";
|
||||
model = "edk131";
|
||||
|
||||
memory@50000000 {
|
||||
device_type = "memory";
|
||||
reg = < 0x50000000 0x10000000 >;
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = "/axi/axi-ethernet@82780000";
|
||||
serial0 = "/axi/serial@83e00000";
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = " console=ttyS0,115200 ";
|
||||
stdout-path = "/axi/serial@83e00000";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = < 0x01 >;
|
||||
#cpus = < 0x01 >;
|
||||
#size-cells = < 0x00 >;
|
||||
|
||||
cpu@0 {
|
||||
clock-frequency = < 0xbebc200 >;
|
||||
compatible = "xlnx,microblaze-8.10.a";
|
||||
d-cache-baseaddr = < 0x50000000 >;
|
||||
d-cache-highaddr = < 0x5fffffff >;
|
||||
d-cache-line-size = < 0x20 >;
|
||||
d-cache-size = < 0x800 >;
|
||||
device_type = "cpu";
|
||||
i-cache-baseaddr = < 0x50000000 >;
|
||||
i-cache-highaddr = < 0x5fffffff >;
|
||||
i-cache-line-size = < 0x20 >;
|
||||
i-cache-size = < 0x800 >;
|
||||
model = "microblaze,8.10.a";
|
||||
reg = < 0x00 >;
|
||||
timebase-frequency = < 0xbebc200 >;
|
||||
xlnx,addr-tag-bits = < 0x11 >;
|
||||
xlnx,allow-dcache-wr = < 0x01 >;
|
||||
xlnx,allow-icache-wr = < 0x01 >;
|
||||
xlnx,area-optimized = < 0x00 >;
|
||||
xlnx,branch-target-cache-size = < 0x00 >;
|
||||
xlnx,cache-byte-size = < 0x800 >;
|
||||
xlnx,d-axi = < 0x01 >;
|
||||
xlnx,d-lmb = < 0x01 >;
|
||||
xlnx,d-plb = < 0x00 >;
|
||||
xlnx,data-size = < 0x20 >;
|
||||
xlnx,dcache-addr-tag = < 0x11 >;
|
||||
xlnx,dcache-always-used = < 0x01 >;
|
||||
xlnx,dcache-byte-size = < 0x800 >;
|
||||
xlnx,dcache-data-width = < 0x00 >;
|
||||
xlnx,dcache-force-tag-lutram = < 0x00 >;
|
||||
xlnx,dcache-interface = < 0x01 >;
|
||||
xlnx,dcache-line-len = < 0x08 >;
|
||||
xlnx,dcache-use-fsl = < 0x00 >;
|
||||
xlnx,dcache-use-writeback = < 0x01 >;
|
||||
xlnx,dcache-victims = < 0x00 >;
|
||||
xlnx,debug-enabled = < 0x01 >;
|
||||
xlnx,div-zero-exception = < 0x01 >;
|
||||
xlnx,dynamic-bus-sizing = < 0x01 >;
|
||||
xlnx,ecc-use-ce-exception = < 0x00 >;
|
||||
xlnx,edge-is-positive = < 0x01 >;
|
||||
xlnx,endianness = < 0x01 >;
|
||||
xlnx,family = "virtex6";
|
||||
xlnx,fault-tolerant = < 0x00 >;
|
||||
xlnx,fpu-exception = < 0x01 >;
|
||||
xlnx,freq = < 0xbebc200 >;
|
||||
xlnx,fsl-data-size = < 0x20 >;
|
||||
xlnx,fsl-exception = < 0x00 >;
|
||||
xlnx,fsl-links = < 0x00 >;
|
||||
xlnx,i-axi = < 0x01 >;
|
||||
xlnx,i-lmb = < 0x01 >;
|
||||
xlnx,i-plb = < 0x00 >;
|
||||
xlnx,icache-always-used = < 0x01 >;
|
||||
xlnx,icache-data-width = < 0x00 >;
|
||||
xlnx,icache-force-tag-lutram = < 0x00 >;
|
||||
xlnx,icache-interface = < 0x00 >;
|
||||
xlnx,icache-line-len = < 0x08 >;
|
||||
xlnx,icache-streams = < 0x00 >;
|
||||
xlnx,icache-use-fsl = < 0x00 >;
|
||||
xlnx,icache-victims = < 0x00 >;
|
||||
xlnx,ill-opcode-exception = < 0x01 >;
|
||||
xlnx,instance = "microblaze_0";
|
||||
xlnx,interconnect = < 0x02 >;
|
||||
xlnx,interrupt-is-edge = < 0x00 >;
|
||||
xlnx,mmu-dtlb-size = < 0x04 >;
|
||||
xlnx,mmu-itlb-size = < 0x02 >;
|
||||
xlnx,mmu-privileged-instr = < 0x00 >;
|
||||
xlnx,mmu-tlb-access = < 0x03 >;
|
||||
xlnx,mmu-zones = < 0x02 >;
|
||||
xlnx,number-of-pc-brk = < 0x01 >;
|
||||
xlnx,number-of-rd-addr-brk = < 0x00 >;
|
||||
xlnx,number-of-wr-addr-brk = < 0x00 >;
|
||||
xlnx,opcode-0x0-illegal = < 0x01 >;
|
||||
xlnx,optimization = < 0x00 >;
|
||||
xlnx,pvr = < 0x02 >;
|
||||
xlnx,pvr-user1 = < 0x00 >;
|
||||
xlnx,pvr-user2 = < 0x00 >;
|
||||
xlnx,reset-msr = < 0x00 >;
|
||||
xlnx,sco = < 0x00 >;
|
||||
xlnx,stream-interconnect = < 0x00 >;
|
||||
xlnx,unaligned-exceptions = < 0x01 >;
|
||||
xlnx,use-barrel = < 0x01 >;
|
||||
xlnx,use-branch-target-cache = < 0x00 >;
|
||||
xlnx,use-dcache = < 0x01 >;
|
||||
xlnx,use-div = < 0x01 >;
|
||||
xlnx,use-ext-brk = < 0x01 >;
|
||||
xlnx,use-ext-nm-brk = < 0x01 >;
|
||||
xlnx,use-extended-fsl-instr = < 0x00 >;
|
||||
xlnx,use-fpu = < 0x01 >;
|
||||
xlnx,use-hw-mul = < 0x02 >;
|
||||
xlnx,use-icache = < 0x01 >;
|
||||
xlnx,use-interrupt = < 0x01 >;
|
||||
xlnx,use-mmu = < 0x03 >;
|
||||
xlnx,use-msr-instr = < 0x01 >;
|
||||
xlnx,use-pcmp-instr = < 0x01 >;
|
||||
xlnx,use-stack-protection = < 0x00 >;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
#address-cells = < 0x01 >;
|
||||
#size-cells = < 0x01 >;
|
||||
compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus";
|
||||
ranges;
|
||||
|
||||
axi-ethernet@82780000 {
|
||||
axistream-connected = < &axi_dma >;
|
||||
compatible = "xlnx,axi-ethernet-2.01.a\0xlnx,axi-ethernet-1.00.a";
|
||||
device_type = "network";
|
||||
interrupt-parent = < &intc >;
|
||||
interrupts = < 0x03 0x02 >;
|
||||
local-mac-address = [ 00 0a 35 00 22 01 ];
|
||||
phy-handle = < &phy7 >;
|
||||
reg = < 0x82780000 0x40000 >;
|
||||
xlnx,avb = < 0x00 >;
|
||||
xlnx,halfdup = < 0x00 >;
|
||||
xlnx,include-io = < 0x01 >;
|
||||
xlnx,mcast-extend = < 0x00 >;
|
||||
xlnx,phy-type = < 0x01 >;
|
||||
xlnx,phyaddr = "0B00001";
|
||||
xlnx,rxcsum = < 0x00 >;
|
||||
xlnx,rxmem = < 0x1000 >;
|
||||
xlnx,rxvlan-strp = < 0x00 >;
|
||||
xlnx,rxvlan-tag = < 0x00 >;
|
||||
xlnx,rxvlan-tran = < 0x00 >;
|
||||
xlnx,stats = < 0x00 >;
|
||||
xlnx,txcsum = < 0x00 >;
|
||||
xlnx,txmem = < 0x1000 >;
|
||||
xlnx,txvlan-strp = < 0x00 >;
|
||||
xlnx,txvlan-tag = < 0x00 >;
|
||||
xlnx,txvlan-tran = < 0x00 >;
|
||||
xlnx,type = < 0x02 >;
|
||||
|
||||
mdio {
|
||||
#address-cells = < 0x01 >;
|
||||
#size-cells = < 0x00 >;
|
||||
|
||||
phy7: phy@7 {
|
||||
compatible = "marvell,88e1111";
|
||||
device_type = "ethernet-phy";
|
||||
reg = < 0x07 >;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
axi_dma: axi-dma@84600000 {
|
||||
compatible = "xlnx,axi-dma-3.00.a";
|
||||
interrupt-parent = < &intc >;
|
||||
interrupts = < 0x01 0x02 0x00 0x02 >;
|
||||
reg = < 0x84600000 0x10000 >;
|
||||
xlnx,dlytmr-resolution = < 0x4e2 >;
|
||||
xlnx,family = "virtex6";
|
||||
xlnx,include-mm2s = < 0x01 >;
|
||||
xlnx,include-mm2s-dre = < 0x01 >;
|
||||
xlnx,include-s2mm = < 0x01 >;
|
||||
xlnx,include-s2mm-dre = < 0x01 >;
|
||||
xlnx,mm2s-burst-size = < 0x10 >;
|
||||
xlnx,prmry-is-aclk-async = < 0x00 >;
|
||||
xlnx,s2mm-burst-size = < 0x10 >;
|
||||
xlnx,sg-include-desc-queue = < 0x01 >;
|
||||
xlnx,sg-include-stscntrl-strm = < 0x01 >;
|
||||
xlnx,sg-length-width = < 0x10 >;
|
||||
xlnx,sg-use-stsapp-length = < 0x01 >;
|
||||
};
|
||||
|
||||
serial@83e00000 {
|
||||
clock-frequency = < 0x5f5e100 >;
|
||||
compatible = "xlnx,axi-uart16550-1.01.a\0xlnx,xps-uart16550-2.00.a\0ns16550a";
|
||||
current-speed = < 0x2580 >;
|
||||
device_type = "serial";
|
||||
interrupt-parent = < &intc >;
|
||||
interrupts = < 0x05 0x02 >;
|
||||
reg = < 0x83e00000 0x10000 >;
|
||||
reg-offset = < 0x1000 >;
|
||||
reg-shift = < 0x02 >;
|
||||
xlnx,external-xin-clk-hz = < 0x17d7840 >;
|
||||
xlnx,family = "virtex6";
|
||||
xlnx,has-external-rclk = < 0x00 >;
|
||||
xlnx,has-external-xin = < 0x00 >;
|
||||
xlnx,is-a-16550 = < 0x01 >;
|
||||
xlnx,use-modem-ports = < 0x00 >;
|
||||
xlnx,use-user-ports = < 0x00 >;
|
||||
};
|
||||
|
||||
system-timer@83c00000 {
|
||||
clock-frequency = < 0x5f5e100 >;
|
||||
compatible = "xlnx,axi-timer-1.01.a\0xlnx,xps-timer-1.00.a";
|
||||
interrupt-parent = < &intc >;
|
||||
interrupts = < 0x02 0x00 >;
|
||||
reg = < 0x83c00000 0x10000 >;
|
||||
xlnx,count-width = < 0x20 >;
|
||||
xlnx,family = "virtex6";
|
||||
xlnx,gen0-assert = < 0x01 >;
|
||||
xlnx,gen1-assert = < 0x01 >;
|
||||
xlnx,one-timer-only = < 0x00 >;
|
||||
xlnx,trig0-assert = < 0x01 >;
|
||||
xlnx,trig1-assert = < 0x01 >;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@81800000 {
|
||||
#interrupt-cells = < 0x02 >;
|
||||
compatible = "xlnx,axi-intc-1.01.a\0xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller;
|
||||
reg = < 0x81800000 0x10000 >;
|
||||
xlnx,kind-of-intr = < 0x04 >;
|
||||
xlnx,num-intr-inputs = < 0x06 >;
|
||||
};
|
||||
|
||||
flash@86000000 {
|
||||
#address-cells = < 0x01 >;
|
||||
#size-cells = < 0x01 >;
|
||||
bank-width = < 0x02 >;
|
||||
compatible = "xlnx,axi-emc-1.01.a\0cfi-flash";
|
||||
reg = < 0x86000000 0x2000000 >;
|
||||
xlnx,axi-clk-period-ps = < 0x2710 >;
|
||||
xlnx,family = "virtex6";
|
||||
xlnx,include-datawidth-matching-0 = < 0x01 >;
|
||||
xlnx,include-datawidth-matching-1 = < 0x00 >;
|
||||
xlnx,include-datawidth-matching-2 = < 0x00 >;
|
||||
xlnx,include-datawidth-matching-3 = < 0x00 >;
|
||||
xlnx,include-negedge-ioregs = < 0x00 >;
|
||||
xlnx,max-mem-width = < 0x10 >;
|
||||
xlnx,mem0-type = < 0x02 >;
|
||||
xlnx,mem0-width = < 0x10 >;
|
||||
xlnx,mem1-type = < 0x00 >;
|
||||
xlnx,mem1-width = < 0x20 >;
|
||||
xlnx,mem2-type = < 0x00 >;
|
||||
xlnx,mem2-width = < 0x20 >;
|
||||
xlnx,mem3-type = < 0x00 >;
|
||||
xlnx,mem3-width = < 0x20 >;
|
||||
xlnx,num-banks-mem = < 0x01 >;
|
||||
xlnx,parity-type-mem-0 = < 0x00 >;
|
||||
xlnx,parity-type-mem-1 = < 0x00 >;
|
||||
xlnx,parity-type-mem-2 = < 0x00 >;
|
||||
xlnx,parity-type-mem-3 = < 0x00 >;
|
||||
xlnx,s-axi-en-reg = < 0x00 >;
|
||||
xlnx,s-axi-mem-addr-width = < 0x20 >;
|
||||
xlnx,s-axi-mem-data-width = < 0x20 >;
|
||||
xlnx,s-axi-mem-id-width = < 0x01 >;
|
||||
xlnx,s-axi-mem-protocol = "AXI4LITE";
|
||||
xlnx,s-axi-reg-addr-width = < 0x20 >;
|
||||
xlnx,s-axi-reg-data-width = < 0x20 >;
|
||||
xlnx,s-axi-reg-protocol = "axi4";
|
||||
xlnx,synch-pipedelay-0 = < 0x02 >;
|
||||
xlnx,synch-pipedelay-1 = < 0x02 >;
|
||||
xlnx,synch-pipedelay-2 = < 0x02 >;
|
||||
xlnx,synch-pipedelay-3 = < 0x02 >;
|
||||
xlnx,tavdv-ps-mem-0 = < 0x1fbd0 >;
|
||||
xlnx,tavdv-ps-mem-1 = < 0x3a98 >;
|
||||
xlnx,tavdv-ps-mem-2 = < 0x3a98 >;
|
||||
xlnx,tavdv-ps-mem-3 = < 0x3a98 >;
|
||||
xlnx,tcedv-ps-mem-0 = < 0x1fbd0 >;
|
||||
xlnx,tcedv-ps-mem-1 = < 0x3a98 >;
|
||||
xlnx,tcedv-ps-mem-2 = < 0x3a98 >;
|
||||
xlnx,tcedv-ps-mem-3 = < 0x3a98 >;
|
||||
xlnx,thzce-ps-mem-0 = < 0x88b8 >;
|
||||
xlnx,thzce-ps-mem-1 = < 0x1b58 >;
|
||||
xlnx,thzce-ps-mem-2 = < 0x1b58 >;
|
||||
xlnx,thzce-ps-mem-3 = < 0x1b58 >;
|
||||
xlnx,thzoe-ps-mem-0 = < 0x1b58 >;
|
||||
xlnx,thzoe-ps-mem-1 = < 0x1b58 >;
|
||||
xlnx,thzoe-ps-mem-2 = < 0x1b58 >;
|
||||
xlnx,thzoe-ps-mem-3 = < 0x1b58 >;
|
||||
xlnx,tlzwe-ps-mem-0 = < 0x88b8 >;
|
||||
xlnx,tlzwe-ps-mem-1 = < 0x00 >;
|
||||
xlnx,tlzwe-ps-mem-2 = < 0x00 >;
|
||||
xlnx,tlzwe-ps-mem-3 = < 0x00 >;
|
||||
xlnx,tpacc-ps-flash-0 = < 0x61a8 >;
|
||||
xlnx,tpacc-ps-flash-1 = < 0x61a8 >;
|
||||
xlnx,tpacc-ps-flash-2 = < 0x61a8 >;
|
||||
xlnx,tpacc-ps-flash-3 = < 0x61a8 >;
|
||||
xlnx,twc-ps-mem-0 = < 0x32c8 >;
|
||||
xlnx,twc-ps-mem-1 = < 0x3a98 >;
|
||||
xlnx,twc-ps-mem-2 = < 0x3a98 >;
|
||||
xlnx,twc-ps-mem-3 = < 0x3a98 >;
|
||||
xlnx,twp-ps-mem-0 = < 0x11170 >;
|
||||
xlnx,twp-ps-mem-1 = < 0x2ee0 >;
|
||||
xlnx,twp-ps-mem-2 = < 0x2ee0 >;
|
||||
xlnx,twp-ps-mem-3 = < 0x2ee0 >;
|
||||
xlnx,twph-ps-mem-0 = < 0x2ee0 >;
|
||||
xlnx,twph-ps-mem-1 = < 0x2ee0 >;
|
||||
xlnx,twph-ps-mem-2 = < 0x2ee0 >;
|
||||
xlnx,twph-ps-mem-3 = < 0x2ee0 >;
|
||||
|
||||
partition@0 {
|
||||
label = "fpga";
|
||||
reg = < 0x00 0x100000 >;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "boot";
|
||||
reg = < 0x100000 0x40000 >;
|
||||
};
|
||||
|
||||
partition@140000 {
|
||||
label = "bootenv";
|
||||
reg = < 0x140000 0x20000 >;
|
||||
};
|
||||
|
||||
partition@160000 {
|
||||
label = "config";
|
||||
reg = < 0x160000 0x20000 >;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "image";
|
||||
reg = < 0x180000 0xa00000 >;
|
||||
};
|
||||
|
||||
partition@b80000 {
|
||||
label = "spare";
|
||||
reg = < 0xb80000 0x00 >;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Binary file not shown.
@@ -0,0 +1,282 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Xilinx Inc.
|
||||
* Written by Edgar E. Iglesias <[email protected]>.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x01>;
|
||||
compatible = "xlnx,microblaze";
|
||||
model = "testing";
|
||||
|
||||
memory@90000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x90000000 0x8000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyUL0,115200";
|
||||
stdout-path = "/plb/serial@84000000";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
#cpus = <0x01>;
|
||||
|
||||
cpu@0 {
|
||||
clock-frequency = <0x3b9aca0>;
|
||||
compatible = "xlnx,microblaze-7.10.d";
|
||||
d-cache-baseaddr = <0x90000000>;
|
||||
d-cache-highaddr = <0x97ffffff>;
|
||||
d-cache-line-size = <0x10>;
|
||||
d-cache-size = <0x800>;
|
||||
device_type = "cpu";
|
||||
i-cache-baseaddr = <0x90000000>;
|
||||
i-cache-highaddr = <0x97ffffff>;
|
||||
i-cache-line-size = <0x10>;
|
||||
i-cache-size = <0x800>;
|
||||
model = "microblaze,7.10.d";
|
||||
reg = <0x00>;
|
||||
timebase-frequency = <0x3b9aca0>;
|
||||
xlnx,addr-tag-bits = <0x10>;
|
||||
xlnx,allow-dcache-wr = <0x01>;
|
||||
xlnx,allow-icache-wr = <0x01>;
|
||||
xlnx,area-optimized = <0x00>;
|
||||
xlnx,cache-byte-size = <0x800>;
|
||||
xlnx,d-lmb = <0x01>;
|
||||
xlnx,d-opb = <0x00>;
|
||||
xlnx,d-plb = <0x01>;
|
||||
xlnx,data-size = <0x20>;
|
||||
xlnx,dcache-addr-tag = <0x10>;
|
||||
xlnx,dcache-always-used = <0x00>;
|
||||
xlnx,dcache-byte-size = <0x800>;
|
||||
xlnx,dcache-line-len = <0x04>;
|
||||
xlnx,dcache-use-fsl = <0x01>;
|
||||
xlnx,debug-enabled = <0x01>;
|
||||
xlnx,div-zero-exception = <0x00>;
|
||||
xlnx,dopb-bus-exception = <0x00>;
|
||||
xlnx,dynamic-bus-sizing = <0x01>;
|
||||
xlnx,edge-is-positive = <0x01>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,fpu-exception = <0x00>;
|
||||
xlnx,fsl-data-size = <0x20>;
|
||||
xlnx,fsl-exception = <0x00>;
|
||||
xlnx,fsl-links = <0x00>;
|
||||
xlnx,i-lmb = <0x01>;
|
||||
xlnx,i-opb = <0x00>;
|
||||
xlnx,i-plb = <0x01>;
|
||||
xlnx,icache-always-used = <0x00>;
|
||||
xlnx,icache-line-len = <0x04>;
|
||||
xlnx,icache-use-fsl = <0x01>;
|
||||
xlnx,ill-opcode-exception = <0x00>;
|
||||
xlnx,instance = "microblaze_0";
|
||||
xlnx,interconnect = <0x01>;
|
||||
xlnx,interrupt-is-edge = <0x00>;
|
||||
xlnx,iopb-bus-exception = <0x00>;
|
||||
xlnx,mmu-dtlb-size = <0x04>;
|
||||
xlnx,mmu-itlb-size = <0x02>;
|
||||
xlnx,mmu-tlb-access = <0x03>;
|
||||
xlnx,mmu-zones = <0x10>;
|
||||
xlnx,number-of-pc-brk = <0x03>;
|
||||
xlnx,number-of-rd-addr-brk = <0x02>;
|
||||
xlnx,number-of-wr-addr-brk = <0x02>;
|
||||
xlnx,opcode-0x0-illegal = <0x00>;
|
||||
xlnx,pvr = <0x01>;
|
||||
xlnx,pvr-user1 = <0x00>;
|
||||
xlnx,pvr-user2 = <0x00>;
|
||||
xlnx,reset-msr = <0x00>;
|
||||
xlnx,sco = <0x00>;
|
||||
xlnx,unaligned-exceptions = <0x01>;
|
||||
xlnx,use-barrel = <0x01>;
|
||||
xlnx,use-dcache = <0x01>;
|
||||
xlnx,use-div = <0x00>;
|
||||
xlnx,use-ext-brk = <0x01>;
|
||||
xlnx,use-ext-nm-brk = <0x01>;
|
||||
xlnx,use-extended-fsl-instr = <0x00>;
|
||||
xlnx,use-fpu = <0x00>;
|
||||
xlnx,use-hw-mul = <0x01>;
|
||||
xlnx,use-icache = <0x01>;
|
||||
xlnx,use-interrupt = <0x01>;
|
||||
xlnx,use-mmu = <0x03>;
|
||||
xlnx,use-msr-instr = <0x01>;
|
||||
xlnx,use-pcmp-instr = <0x01>;
|
||||
};
|
||||
};
|
||||
|
||||
plb {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x01>;
|
||||
compatible = "xlnx,plb-v46-1.03.a\0simple-bus";
|
||||
ranges;
|
||||
|
||||
ethernet@81000000 {
|
||||
compatible = "xlnx,xps-ethernetlite-2.00.a";
|
||||
device_type = "network";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x01 0x00>;
|
||||
local-mac-address = [02 00 00 00 00 00];
|
||||
reg = <0x81000000 0x10000>;
|
||||
xlnx,duplex = <0x01>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,rx-ping-pong = <0x00>;
|
||||
xlnx,tx-ping-pong = <0x00>;
|
||||
};
|
||||
|
||||
flash@a0000000 {
|
||||
bank-width = <0x01>;
|
||||
compatible = "xlnx,xps-mch-emc-2.00.a\0cfi-flash";
|
||||
reg = <0xa0000000 0x1000000>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,include-datawidth-matching-0 = <0x01>;
|
||||
xlnx,include-datawidth-matching-1 = <0x00>;
|
||||
xlnx,include-datawidth-matching-2 = <0x00>;
|
||||
xlnx,include-datawidth-matching-3 = <0x00>;
|
||||
xlnx,include-negedge-ioregs = <0x00>;
|
||||
xlnx,include-plb-ipif = <0x01>;
|
||||
xlnx,include-wrbuf = <0x01>;
|
||||
xlnx,max-mem-width = <0x08>;
|
||||
xlnx,mch-native-dwidth = <0x20>;
|
||||
xlnx,mch-plb-clk-period-ps = <0x3e80>;
|
||||
xlnx,mch-splb-awidth = <0x20>;
|
||||
xlnx,mch0-accessbuf-depth = <0x10>;
|
||||
xlnx,mch0-protocol = <0x00>;
|
||||
xlnx,mch0-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch1-accessbuf-depth = <0x10>;
|
||||
xlnx,mch1-protocol = <0x00>;
|
||||
xlnx,mch1-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch2-accessbuf-depth = <0x10>;
|
||||
xlnx,mch2-protocol = <0x00>;
|
||||
xlnx,mch2-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch3-accessbuf-depth = <0x10>;
|
||||
xlnx,mch3-protocol = <0x00>;
|
||||
xlnx,mch3-rddatabuf-depth = <0x10>;
|
||||
xlnx,mem0-width = <0x08>;
|
||||
xlnx,mem1-width = <0x20>;
|
||||
xlnx,mem2-width = <0x20>;
|
||||
xlnx,mem3-width = <0x20>;
|
||||
xlnx,num-banks-mem = <0x01>;
|
||||
xlnx,num-channels = <0x00>;
|
||||
xlnx,priority-mode = <0x00>;
|
||||
xlnx,synch-mem-0 = <0x00>;
|
||||
xlnx,synch-mem-1 = <0x00>;
|
||||
xlnx,synch-mem-2 = <0x00>;
|
||||
xlnx,synch-mem-3 = <0x00>;
|
||||
xlnx,synch-pipedelay-0 = <0x02>;
|
||||
xlnx,synch-pipedelay-1 = <0x02>;
|
||||
xlnx,synch-pipedelay-2 = <0x02>;
|
||||
xlnx,synch-pipedelay-3 = <0x02>;
|
||||
xlnx,tavdv-ps-mem-0 = <0x11170>;
|
||||
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-0 = <0x11170>;
|
||||
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,thzce-ps-mem-0 = <0x61a8>;
|
||||
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-0 = <0x61a8>;
|
||||
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
||||
xlnx,tlzwe-ps-mem-0 = <0x1388>;
|
||||
xlnx,tlzwe-ps-mem-1 = <0x00>;
|
||||
xlnx,tlzwe-ps-mem-2 = <0x00>;
|
||||
xlnx,tlzwe-ps-mem-3 = <0x00>;
|
||||
xlnx,twc-ps-mem-0 = <0x11170>;
|
||||
xlnx,twc-ps-mem-1 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-2 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-3 = <0x3a98>;
|
||||
xlnx,twp-ps-mem-0 = <0xafc8>;
|
||||
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
||||
xlnx,xcl0-linesize = <0x04>;
|
||||
xlnx,xcl0-writexfer = <0x01>;
|
||||
xlnx,xcl1-linesize = <0x04>;
|
||||
xlnx,xcl1-writexfer = <0x01>;
|
||||
xlnx,xcl2-linesize = <0x04>;
|
||||
xlnx,xcl2-writexfer = <0x01>;
|
||||
xlnx,xcl3-linesize = <0x04>;
|
||||
xlnx,xcl3-writexfer = <0x01>;
|
||||
};
|
||||
|
||||
gpio@81400000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x02 0x02>;
|
||||
reg = <0x81400000 0x10000>;
|
||||
xlnx,all-inputs = <0x00>;
|
||||
xlnx,all-inputs-2 = <0x00>;
|
||||
xlnx,dout-default = <0x00>;
|
||||
xlnx,dout-default-2 = <0x00>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,gpio-width = <0x08>;
|
||||
xlnx,interrupt-present = <0x01>;
|
||||
xlnx,is-bidir = <0x00>;
|
||||
xlnx,is-bidir-2 = <0x01>;
|
||||
xlnx,is-dual = <0x00>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
};
|
||||
|
||||
serial@84000000 {
|
||||
clock-frequency = <0x3b9aca0>;
|
||||
compatible = "xlnx,xps-uartlite-1.00.a";
|
||||
current-speed = <0x1c200>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x03 0x00>;
|
||||
port-number = <0x00>;
|
||||
reg = <0x84000000 0x10000>;
|
||||
xlnx,baudrate = <0x1c200>;
|
||||
xlnx,data-bits = <0x08>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,odd-parity = <0x00>;
|
||||
xlnx,use-parity = <0x00>;
|
||||
};
|
||||
|
||||
debug@84400000 {
|
||||
compatible = "xlnx,mdm-1.00.d";
|
||||
reg = <0x84400000 0x10000>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,interconnect = <0x01>;
|
||||
xlnx,jtag-chain = <0x02>;
|
||||
xlnx,mb-dbg-ports = <0x01>;
|
||||
xlnx,uart-width = <0x08>;
|
||||
xlnx,use-uart = <0x01>;
|
||||
xlnx,write-fsl-ports = <0x00>;
|
||||
};
|
||||
|
||||
interrupt-controller@81800000 {
|
||||
#interrupt-cells = <0x02>;
|
||||
compatible = "xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller;
|
||||
reg = <0x81800000 0x10000>;
|
||||
xlnx,kind-of-intr = <0x0a>;
|
||||
xlnx,num-intr-inputs = <0x04>;
|
||||
linux,phandle = <0x01>;
|
||||
};
|
||||
|
||||
timer@83c00000 {
|
||||
compatible = "xlnx,xps-timer-1.00.a";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x02>;
|
||||
reg = <0x83c00000 0x10000>;
|
||||
xlnx,count-width = <0x20>;
|
||||
xlnx,family = "spartan3adsp";
|
||||
xlnx,gen0-assert = <0x01>;
|
||||
xlnx,gen1-assert = <0x01>;
|
||||
xlnx,one-timer-only = <0x00>;
|
||||
xlnx,trig0-assert = <0x01>;
|
||||
xlnx,trig1-assert = <0x01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user