Import QEMU upstream snapshot d2e570c
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
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/* SPDX-License-Identifier: MIT */
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/*
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* Define LoongArch target-specific constraint sets.
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*
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*
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* Based on tcg/riscv/tcg-target-con-set.h
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*
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(rz, r)
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C_O0_I2(r, rz)
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C_O0_I2(w, r)
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C_O0_I3(r, r, r)
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C_O1_I1(r, r)
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C_O1_I1(w, r)
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C_O1_I1(w, w)
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C_O1_I2(r, r, r)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rJ)
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C_O1_I2(r, r, rU)
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C_O1_I2(r, r, rW)
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C_O1_I2(r, 0, rz)
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C_O1_I2(w, w, w)
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C_O1_I2(w, w, wM)
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C_O1_I2(w, w, wA)
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C_O1_I3(w, w, w, w)
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C_O1_I4(r, r, rJ, rz, rz)
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C_N2_I1(r, r, r)
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/* SPDX-License-Identifier: MIT */
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/*
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* Define LoongArch target-specific operand constraints.
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*
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*
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* Based on tcg/riscv/tcg-target-con-str.h
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*
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('w', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S12)
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CONST('J', TCG_CT_CONST_S32)
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CONST('U', TCG_CT_CONST_U12)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('M', TCG_CT_CONST_VCMP)
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CONST('A', TCG_CT_CONST_VADD)
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific opcode support
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*/
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#ifndef TCG_TARGET_HAS_H
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#define TCG_TARGET_HAS_H
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#include "host/cpuinfo.h"
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/* 64-bit operations */
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)
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#define TCG_TARGET_HAS_tst 0
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#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX)
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#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX)
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#define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX)
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec 1
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#define TCG_TARGET_HAS_nand_vec 0
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#define TCG_TARGET_HAS_nor_vec 1
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#define TCG_TARGET_HAS_eqv_vec 0
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_roti_vec 1
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 0
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#define TCG_TARGET_extract_valid(type, ofs, len) 1
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#define TCG_TARGET_deposit_valid(type, ofs, len) 1
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static inline bool
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tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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return true;
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}
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return ofs == 0 && (len == 8 || len == 16);
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}
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#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
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#endif
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific memory model
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*/
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#ifndef TCG_TARGET_MO_H
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#define TCG_TARGET_MO_H
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#define TCG_TARGET_DEFAULT_MO 0
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#endif
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/*
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* Copyright (c) 2023 Jiajie Chen
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or
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* (at your option) any later version.
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*
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* See the COPYING file in the top-level directory for details.
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*
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* Target-specific opcodes for host vector expansion. These will be
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* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
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* consider these to be UNSPEC with names.
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*/
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*
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* Based on tcg/riscv/tcg-target.h
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*
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* Copyright (c) 2018 SiFive, Inc
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef LOONGARCH_TCG_TARGET_H
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#define LOONGARCH_TCG_TARGET_H
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_NB_REGS 64
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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typedef enum {
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TCG_REG_ZERO,
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TCG_REG_RA,
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TCG_REG_TP,
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TCG_REG_SP,
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TCG_REG_A0,
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TCG_REG_A1,
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TCG_REG_A2,
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TCG_REG_A3,
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TCG_REG_A4,
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TCG_REG_A5,
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TCG_REG_A6,
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TCG_REG_A7,
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TCG_REG_T0,
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TCG_REG_T1,
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TCG_REG_T2,
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TCG_REG_T3,
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TCG_REG_T4,
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TCG_REG_T5,
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TCG_REG_T6,
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TCG_REG_T7,
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TCG_REG_T8,
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TCG_REG_RESERVED,
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TCG_REG_S9,
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TCG_REG_S0,
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_S8,
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TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
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TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
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TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
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TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
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TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
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TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
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TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
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TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
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/* aliases */
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TCG_AREG0 = TCG_REG_S0,
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TCG_REG_TMP0 = TCG_REG_T8,
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TCG_REG_TMP1 = TCG_REG_T7,
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TCG_REG_TMP2 = TCG_REG_T6,
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TCG_VEC_TMP0 = TCG_REG_V23,
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} TCGReg;
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#define TCG_REG_ZERO TCG_REG_ZERO
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#endif /* LOONGARCH_TCG_TARGET_H */
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