Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
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* QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
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* bitmanip extension v0.93.
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*
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* Copyright (c) 2023 Rivos Inc
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "disas/riscv.h"
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#include "disas/riscv-xlrbr.h"
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#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
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#include "riscv-xlrbr-op.c.inc"
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#undef OP
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const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch ((inst >> 0) & 0b1111111) {
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case 0b0010011:
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switch ((inst >> 12) & 0b111) {
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case 0b001:
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switch ((inst >> 20 & 0b111111111111)) {
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case 0b011000010000:
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return &op_crc32_b;
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case 0b011000010001:
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return &op_crc32_h;
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case 0b011000010010:
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return &op_crc32_w;
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case 0b011000010011:
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return &op_crc32_d;
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case 0b011000011000:
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return &op_crc32c_b;
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case 0b011000011001:
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return &op_crc32c_h;
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case 0b011000011010:
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return &op_crc32c_w;
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case 0b011000011011:
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return &op_crc32c_d;
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}
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break;
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}
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break;
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}
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return NULL;
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}
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