Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
466 lines
13 KiB
C
466 lines
13 KiB
C
/*
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* QEMU RISC-V Disassembler for xthead.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "disas/riscv.h"
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#include "disas/riscv-xthead.h"
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#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
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#include "riscv-xthead-op.c.inc"
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#undef OP
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const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0000000:
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case 0b0000001:
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case 0b0000010:
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case 0b0000011: return &op_th_addsl;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0001010: return &op_th_srriw;
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case 0b1000000:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_tstnbz;
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}
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break;
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case 0b1000001:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_rev;
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}
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break;
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case 0b1000010:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_ff0;
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}
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break;
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case 0b1000011:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_ff1;
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}
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break;
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case 0b1000100:
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case 0b1001000:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_revw;
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}
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break;
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case 0b0001000:
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case 0b0001001:
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return &op_th_srri;
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break;
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}
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break;
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case 2: return &op_th_ext;
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case 3: return &op_th_extu;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 26) & 0b111111) {
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case 0b100010: return &op_th_tst;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 0:
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switch ((inst >> 20 & 0b111111111111)) {
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case 0b000000000001:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_dcache_call;
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}
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break;
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case 0b000000000011:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_dcache_ciall;
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}
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break;
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case 0b000000000010:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_dcache_iall;
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}
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break;
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case 0b000000101001: return &op_th_dcache_cpa;
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case 0b000000101011: return &op_th_dcache_cipa;
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case 0b000000101010: return &op_th_dcache_ipa;
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case 0b000000100101: return &op_th_dcache_cva;
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case 0b000000100111: return &op_th_dcache_civa;
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case 0b000000100110: return &op_th_dcache_iva;
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case 0b000000100001: return &op_th_dcache_csw;
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case 0b000000100011: return &op_th_dcache_cisw;
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case 0b000000100010: return &op_th_dcache_isw;
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case 0b000000101000: return &op_th_dcache_cpal1;
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case 0b000000100100: return &op_th_dcache_cval1;
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case 0b000000010000:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_icache_iall;
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}
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break;
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case 0b000000010001:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_icache_ialls;
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}
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break;
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case 0b000000111000: return &op_th_icache_ipa;
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case 0b000000110000: return &op_th_icache_iva;
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case 0b000000010101:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_l2cache_call;
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}
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break;
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case 0b000000010111:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_l2cache_ciall;
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}
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break;
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case 0b000000010110:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_l2cache_iall;
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}
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break;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0100000: return &op_th_mveqz;
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case 0b0100001: return &op_th_mvnez;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 6:
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switch ((inst >> 27) & 0b11111) {
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case 8: return &op_th_flrw;
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case 10: return &op_th_flurw;
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case 12: return &op_th_flrd;
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case 14: return &op_th_flurd;
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}
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break;
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case 7:
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switch ((inst >> 27) & 0b11111) {
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case 8: return &op_th_fsrw;
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case 10: return &op_th_fsurw;
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case 12: return &op_th_fsrd;
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case 14: return &op_th_fsurd;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b1010000:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_fmv_hw_x;
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}
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break;
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case 0b1100000:
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if (((inst >> 20) & 0b11111) == 0) {
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return &op_th_fmv_x_hw;
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}
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break;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0010000: return &op_th_mula;
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case 0b0010001: return &op_th_muls;
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case 0b0010010: return &op_th_mulaw;
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case 0b0010011: return &op_th_mulsw;
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case 0b0010100: return &op_th_mulah;
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case 0b0010101: return &op_th_mulsh;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 4:
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switch ((inst >> 27) & 0b11111) {
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case 0: return &op_th_lrb;
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case 1: return &op_th_lbib;
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case 2: return &op_th_lurb;
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case 3: return &op_th_lbia;
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case 4: return &op_th_lrh;
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case 5: return &op_th_lhib;
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case 6: return &op_th_lurh;
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case 7: return &op_th_lhia;
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case 8: return &op_th_lrw;
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case 9: return &op_th_lwib;
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case 10: return &op_th_lurw;
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case 11: return &op_th_lwia;
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case 12: return &op_th_lrd;
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case 13: return &op_th_ldib;
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case 14: return &op_th_lurd;
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case 15: return &op_th_ldia;
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case 16: return &op_th_lrbu;
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case 17: return &op_th_lbuib;
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case 18: return &op_th_lurbu;
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case 19: return &op_th_lbuia;
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case 20: return &op_th_lrhu;
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case 21: return &op_th_lhuib;
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case 22: return &op_th_lurhu;
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case 23: return &op_th_lhuia;
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case 24: return &op_th_lrwu;
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case 25: return &op_th_lwuib;
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case 26: return &op_th_lurwu;
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case 27: return &op_th_lwuia;
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}
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break;
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case 5:
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switch ((inst >> 27) & 0b11111) {
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case 0: return &op_th_srb;
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case 1: return &op_th_sbib;
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case 2: return &op_th_surb;
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case 3: return &op_th_sbia;
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case 4: return &op_th_srh;
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case 5: return &op_th_shib;
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case 6: return &op_th_surh;
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case 7: return &op_th_shia;
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case 8: return &op_th_srw;
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case 9: return &op_th_swib;
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case 10: return &op_th_surw;
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case 11: return &op_th_swia;
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case 12: return &op_th_srd;
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case 13: return &op_th_sdib;
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case 14: return &op_th_surd;
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case 15: return &op_th_sdia;
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}
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break;
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 4:
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switch ((inst >> 27) & 0b11111) {
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case 28: return &op_th_lwd;
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case 30: return &op_th_lwud;
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case 31: return &op_th_ldd;
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}
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break;
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case 5:
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switch ((inst >> 27) & 0b11111) {
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case 28: return &op_th_swd;
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case 31: return &op_th_sdd;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 0:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0000010: return &op_th_sfence_vmas;
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case 0b0000000:
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switch ((inst >> 20) & 0b11111) {
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case 0b11000: return &op_th_sync;
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case 0b11010: return &op_th_sync_i;
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case 0b11011: return &op_th_sync_is;
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case 0b11001: return &op_th_sync_s;
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}
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break;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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return NULL;
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}
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