Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
34 lines
767 B
C
34 lines
767 B
C
/*
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* QEMU RISC-V Disassembler for xventana.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "disas/riscv.h"
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#include "disas/riscv-xventana.h"
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#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
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#include "riscv-xventana-op.c.inc"
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#undef OP
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const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 30:
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switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
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case 6: return &op_vt_maskc;
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case 7: return &op_vt_maskcn;
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}
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break;
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}
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break;
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}
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return NULL;
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}
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