Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
42 lines
1.4 KiB
ReStructuredText
42 lines
1.4 KiB
ReStructuredText
Tenstorrent Atlantis (``tt-atlantis``)
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======================================
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The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
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and CoreLab Technology. It is based on the Atlantis SoC, which includes
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the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
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The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
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RISC-V CPU.
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tt-atlantis QEMU model features
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-------------------------------
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* 8-core Ascalon-X CPU Cluster
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* RISC-V compliant Advanced Interrupt Architecture
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* 16550A compatible UART
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Known limitations
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-----------------
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The QEMU tt-atlantis machine does not yet model every device on the
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real platform. Notably:
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* There is no PCI host bridge, so virtio-pci devices cannot be
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attached. Boots that need block storage must use ``-initrd`` with
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an initramfs.
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* The DesignWare UART is modelled with QEMU's ns16550-compatible
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``serial_mm`` device; DesignWare-specific registers beyond that
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set return 0.
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Supported software
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------------------
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The Tenstorrent Ascalon CPUs avoid proprietary or non-standard
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extensions, so compatibility with existing software is generally
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good. The QEMU tt-atlantis machine works with upstream OpenSBI
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and Linux with default configurations.
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The development board hardware will require some implementation
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specific setup in firmware which is being developed and may
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become a requirement or option for the tt-atlantis machine.
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