Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
140 lines
4.4 KiB
C
140 lines
4.4 KiB
C
/*
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* NXP i.MX 8MM Evaluation Kit System Emulation
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*
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* Copyright (c) 2025, NXP Semiconductors
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* Author: Gaurav Sharma <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "system/address-spaces.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/fsl-imx8mm.h"
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#include "hw/arm/machines-qom.h"
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#include "hw/core/boards.h"
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#include "hw/core/qdev-properties.h"
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#include "system/kvm.h"
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#include "system/qtest.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include <libfdt.h>
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#define TYPE_IMX8MM_EVK_MACHINE MACHINE_TYPE_NAME("imx8mm-evk")
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OBJECT_DECLARE_SIMPLE_TYPE(Imx8mmEvkMachineState, IMX8MM_EVK_MACHINE)
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struct Imx8mmEvkMachineState {
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MachineState parent;
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struct arm_boot_info bootinfo;
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};
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static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *fdt)
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{
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int i, offset;
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/* Temporarily disable following nodes until they are implemented */
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const char *nodes_to_remove[] = {
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"nxp,imx8mm-fspi",
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"fsl,imx8mm-mipi-csi",
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"fsl,imx8mm-mipi-dsim"
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};
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for (i = 0; i < ARRAY_SIZE(nodes_to_remove); i++) {
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const char *dev_str = nodes_to_remove[i];
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offset = fdt_node_offset_by_compatible(fdt, -1, dev_str);
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while (offset >= 0) {
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fdt_nop_node(fdt, offset);
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offset = fdt_node_offset_by_compatible(fdt, offset, dev_str);
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}
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}
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/* Remove cpu-idle-states property from CPU nodes */
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offset = fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a53");
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while (offset >= 0) {
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fdt_nop_property(fdt, offset, "cpu-idle-states");
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offset = fdt_node_offset_by_compatible(fdt, offset, "arm,cortex-a53");
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}
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if (kvm_enabled()) {
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/* Use system counter frequency from host CPU to fix time in guest */
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offset = fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer");
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while (offset >= 0) {
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fdt_nop_property(fdt, offset, "clock-frequency");
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offset = fdt_node_offset_by_compatible(fdt, offset, "arm,armv8-timer");
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}
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}
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}
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static void imx8mm_evk_init(MachineState *machine)
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{
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Imx8mmEvkMachineState *ims = IMX8MM_EVK_MACHINE(machine);
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FslImx8mmState *s;
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if (machine->ram_size > FSL_IMX8MM_RAM_SIZE_MAX) {
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error_report("RAM size " RAM_ADDR_FMT " above max supported (%08" PRIx64 ")",
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machine->ram_size, FSL_IMX8MM_RAM_SIZE_MAX);
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exit(1);
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}
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ims->bootinfo.loader_start = FSL_IMX8MM_RAM_START;
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ims->bootinfo.board_id = -1;
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ims->bootinfo.ram_size = machine->ram_size;
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ims->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
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ims->bootinfo.modify_dtb = imx8mm_evk_modify_dtb;
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s = FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine),
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"soc", &error_fatal, NULL));
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object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
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memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,
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machine->ram);
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for (int i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {
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BusState *bus;
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DeviceState *carddev;
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BlockBackend *blk;
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DriveInfo *di = drive_get(IF_SD, i, 0);
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if (!di) {
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continue;
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}
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blk = blk_by_legacy_dinfo(di);
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bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
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carddev = qdev_new(TYPE_SD_CARD);
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qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
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qdev_realize_and_unref(carddev, bus, &error_fatal);
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}
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if (!qtest_enabled()) {
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arm_load_kernel(&s->cpu[0], machine, &ims->bootinfo);
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}
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}
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static const char *imx8mm_evk_get_default_cpu_type(const MachineState *ms)
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{
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if (kvm_enabled()) {
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return ARM_CPU_TYPE_NAME("host");
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}
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return ARM_CPU_TYPE_NAME("cortex-a53");
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}
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static void imx8mm_evk_machine_init(MachineClass *mc)
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{
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mc->desc = "NXP i.MX 8MM EVK Board";
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mc->init = imx8mm_evk_init;
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mc->max_cpus = FSL_IMX8MM_NUM_CPUS;
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mc->default_cpus = FSL_IMX8MM_NUM_CPUS;
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mc->default_ram_size = 2 * GiB;
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mc->default_ram_id = "imx8mm-evk.ram";
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mc->get_default_cpu_type = imx8mm_evk_get_default_cpu_type;
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}
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DEFINE_MACHINE_EXTENDED("imx8mm-evk", MACHINE, Imx8mmEvkMachineState,
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imx8mm_evk_machine_init, false,
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aarch64_machine_interfaces)
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