Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
342 lines
10 KiB
C
342 lines
10 KiB
C
/*
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* ASPEED Serial GPIO Controller
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*
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* Copyright 2025 Google LLC.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "hw/core/irq.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/gpio/aspeed_sgpio.h"
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/*
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* For each set of gpios there are three sensitivity registers that control
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* the interrupt trigger mode.
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*
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* | 2 | 1 | 0 | trigger mode
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* -----------------------------
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* | 0 | 0 | 0 | falling-edge
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* | 0 | 0 | 1 | rising-edge
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* | 0 | 1 | 0 | level-low
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* | 0 | 1 | 1 | level-high
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* | 1 | X | X | dual-edge
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*/
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/* GPIO Interrupt Triggers */
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#define ASPEED_FALLING_EDGE 0
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#define ASPEED_RISING_EDGE 1
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#define ASPEED_LEVEL_LOW 2
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#define ASPEED_LEVEL_HIGH 3
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#define ASPEED_DUAL_EDGE 4
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static void aspeed_clear_irq(AspeedSGPIOState *s, int idx)
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{
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uint32_t reg_index = idx / 32;
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uint32_t bit_index = idx % 32;
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uint32_t pending = extract32(s->int_regs[reg_index], bit_index, 1);
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assert(s->pending >= pending);
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/* No change to s->pending if pending is 0 */
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s->pending -= pending;
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/*
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* The write acknowledged the interrupt regardless of whether it
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* was pending or not. The post-condition is that it mustn't be
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* pending. Unconditionally clear the status bit.
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*/
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s->int_regs[reg_index] = deposit32(s->int_regs[reg_index], bit_index, 1, 0);
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}
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static void aspeed_evaluate_irq(AspeedSGPIOState *s, int sgpio_prev_high,
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int sgpio_curr_high, int idx)
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{
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uint32_t ctrl = s->ctrl_regs[idx];
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uint32_t falling_edge = 0, rising_edge = 0;
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uint32_t int_trigger = SHARED_FIELD_EX32(ctrl, SGPIO_INT_TYPE);
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uint32_t int_enabled = SHARED_FIELD_EX32(ctrl, SGPIO_INT_EN);
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uint32_t reg_index = idx / 32;
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uint32_t bit_index = idx % 32;
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if (!int_enabled) {
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return;
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}
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/* Detect edges */
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if (sgpio_curr_high && !sgpio_prev_high) {
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rising_edge = 1;
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} else if (!sgpio_curr_high && sgpio_prev_high) {
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falling_edge = 1;
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}
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if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) ||
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((int_trigger == ASPEED_RISING_EDGE) && rising_edge) ||
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((int_trigger == ASPEED_LEVEL_LOW) && !sgpio_curr_high) ||
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((int_trigger == ASPEED_LEVEL_HIGH) && sgpio_curr_high) ||
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((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge)))
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{
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s->int_regs[reg_index] = deposit32(s->int_regs[reg_index],
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bit_index, 1, 1);
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/* Trigger the VIC IRQ */
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s->pending++;
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}
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}
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static void aspeed_sgpio_update(AspeedSGPIOState *s, uint32_t idx,
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uint32_t value)
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{
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uint32_t old = s->ctrl_regs[idx];
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uint32_t new = value;
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uint32_t diff = (old ^ new);
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if (diff) {
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/* If the interrupt clear bit is set */
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if (SHARED_FIELD_EX32(new, SGPIO_INT_STATUS)) {
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aspeed_clear_irq(s, idx);
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/* Clear the interrupt clear bit */
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new &= ~SGPIO_INT_STATUS_MASK;
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}
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/* Update the control register. */
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s->ctrl_regs[idx] = new;
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/* If the output value is changed */
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if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_OUT_VAL)) {
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/* ...trigger the line-state IRQ */
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qemu_set_irq(s->sgpios[idx], 1);
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}
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/* If the input value is changed */
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if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_IN_VAL)) {
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aspeed_evaluate_irq(s,
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SHARED_FIELD_EX32(old, SGPIO_SERIAL_IN_VAL),
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SHARED_FIELD_EX32(new, SGPIO_SERIAL_IN_VAL),
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idx);
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}
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}
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qemu_set_irq(s->irq, !!(s->pending));
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}
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static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s,
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uint32_t reg)
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{
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uint32_t idx = reg - R_SGPIO_INT_STATUS_0;
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if (idx >= ASPEED_SGPIO_MAX_INT) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: interrupt status index: %d, out of bounds\n",
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__func__, idx);
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return 0;
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}
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return s->int_regs[idx];
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}
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static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s,
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uint32_t reg)
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{
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
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uint32_t idx = reg - R_SGPIO_0_CONTROL;
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if (idx >= agc->nr_sgpio_pin_pairs) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n",
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__func__, idx);
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return 0;
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}
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return s->ctrl_regs[idx];
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}
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static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s,
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uint32_t reg, uint64_t data)
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{
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
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uint32_t idx = reg - R_SGPIO_0_CONTROL;
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if (idx >= agc->nr_sgpio_pin_pairs) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n",
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__func__, idx);
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return;
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}
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aspeed_sgpio_update(s, idx, data);
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}
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static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset,
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uint32_t size)
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{
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AspeedSGPIOState *s = ASPEED_SGPIO(opaque);
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uint64_t value = 0;
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uint64_t reg;
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reg = offset >> 2;
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switch (reg) {
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case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7:
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value = aspeed_sgpio_2700_read_int_status_reg(s, reg);
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break;
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case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:
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value = aspeed_sgpio_2700_read_control_reg(s, reg);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
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HWADDR_PRIx"\n", __func__, offset);
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return 0;
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}
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return value;
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}
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static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data,
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uint32_t size)
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{
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AspeedSGPIOState *s = ASPEED_SGPIO(opaque);
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uint64_t reg;
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reg = offset >> 2;
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switch (reg) {
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case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:
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aspeed_sgpio_2700_write_control_reg(s, reg, data);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
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HWADDR_PRIx"\n", __func__, offset);
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return;
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}
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}
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static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin)
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{
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uint32_t value = s->ctrl_regs[pin >> 1];
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bool is_input = !(pin % 2);
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uint32_t bit_mask = 0;
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if (is_input) {
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bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
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} else {
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bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
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}
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return value & bit_mask;
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}
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static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool level)
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{
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uint32_t value = s->ctrl_regs[pin >> 1];
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bool is_input = !(pin % 2);
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uint32_t bit_mask = 0;
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if (is_input) {
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bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
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} else {
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bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
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}
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if (level) {
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value |= bit_mask;
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} else {
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value &= ~bit_mask;
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}
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aspeed_sgpio_update(s, pin >> 1, value);
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}
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static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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bool level = true;
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int pin = 0xfff;
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AspeedSGPIOState *s = ASPEED_SGPIO(obj);
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if (sscanf(name, "sgpio%03d", &pin) != 1) {
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error_setg(errp, "%s: error reading %s", __func__, name);
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return;
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}
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level = aspeed_sgpio_get_pin_level(s, pin);
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visit_type_bool(v, name, &level, errp);
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}
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static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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bool level;
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int pin = 0xfff;
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AspeedSGPIOState *s = ASPEED_SGPIO(obj);
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if (!visit_type_bool(v, name, &level, errp)) {
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return;
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}
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if (sscanf(name, "sgpio%03d", &pin) != 1) {
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error_setg(errp, "%s: error reading %s", __func__, name);
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return;
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}
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aspeed_sgpio_set_pin_level(s, pin, level);
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}
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static const MemoryRegionOps aspeed_sgpio_2700_ops = {
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.read = aspeed_sgpio_2700_read,
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.write = aspeed_sgpio_2700_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void aspeed_sgpio_realize(DeviceState *dev, Error **errp)
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{
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AspeedSGPIOState *s = ASPEED_SGPIO(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
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/* Interrupt parent line */
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s,
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TYPE_ASPEED_SGPIO, agc->mem_size);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void aspeed_sgpio_init(Object *obj)
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{
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for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {
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g_autofree char *name = g_strdup_printf("sgpio%03d", i);
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object_property_add(obj, name, "bool", aspeed_sgpio_get_pin,
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aspeed_sgpio_set_pin, NULL, NULL);
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}
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}
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static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_sgpio_realize;
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dc->desc = "Aspeed SGPIO Controller";
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}
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static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *data)
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{
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AspeedSGPIOClass *agc = ASPEED_SGPIO_CLASS(klass);
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agc->nr_sgpio_pin_pairs = ASPEED_SGPIO_MAX_PIN_PAIR;
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agc->mem_size = 0x1000;
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agc->reg_ops = &aspeed_sgpio_2700_ops;
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}
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static const TypeInfo aspeed_sgpio_types[] = {
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{
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.name = TYPE_ASPEED_SGPIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSGPIOState),
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.class_size = sizeof(AspeedSGPIOClass),
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.class_init = aspeed_sgpio_class_init,
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.abstract = true,
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},
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{
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.name = TYPE_ASPEED_SGPIO "-ast2700",
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.parent = TYPE_ASPEED_SGPIO,
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.class_init = aspeed_sgpio_2700_class_init,
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.instance_init = aspeed_sgpio_init,
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}
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};
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DEFINE_TYPES(aspeed_sgpio_types)
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