Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
468 lines
14 KiB
C
468 lines
14 KiB
C
/*
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* Hexagon TLB QOM Device
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*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/hexagon/hexagon_tlb.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/core/resettable.h"
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#include "migration/vmstate.h"
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#include "monitor/monitor.h"
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#include "qapi/error.h"
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#include "exec/page-protection.h"
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#include "exec/target_page.h"
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#include "target/hexagon/cpu.h"
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#include "target/hexagon/cpu_bits.h"
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/* PTE (TLB entry) field extraction */
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#define GET_PTE_PPD(entry) extract64((entry), 0, 24)
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#define GET_PTE_C(entry) extract64((entry), 24, 4)
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#define GET_PTE_U(entry) extract64((entry), 28, 1)
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#define GET_PTE_R(entry) extract64((entry), 29, 1)
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#define GET_PTE_W(entry) extract64((entry), 30, 1)
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#define GET_PTE_X(entry) extract64((entry), 31, 1)
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#define GET_PTE_VPN(entry) extract64((entry), 32, 20)
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#define GET_PTE_ASID(entry) extract64((entry), 52, 7)
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#define GET_PTE_ATR0(entry) extract64((entry), 59, 1)
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#define GET_PTE_ATR1(entry) extract64((entry), 60, 1)
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#define GET_PTE_PA35(entry) extract64((entry), 61, 1)
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#define GET_PTE_G(entry) extract64((entry), 62, 1)
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#define GET_PTE_V(entry) extract64((entry), 63, 1)
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/* PPD (physical page descriptor) */
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static inline uint64_t GET_PPD(uint64_t entry)
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{
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return GET_PTE_PPD(entry) | (GET_PTE_PA35(entry) << 24);
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}
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#define NO_ASID (1 << 8)
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typedef enum {
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PGSIZE_4K,
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PGSIZE_16K,
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PGSIZE_64K,
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PGSIZE_256K,
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PGSIZE_1M,
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PGSIZE_4M,
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PGSIZE_16M,
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PGSIZE_64M,
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PGSIZE_256M,
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PGSIZE_1G,
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} tlb_pgsize_t;
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#define NUM_PGSIZE_TYPES (PGSIZE_1G + 1)
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static const char *pgsize_str[NUM_PGSIZE_TYPES] = {
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"4K",
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"16K",
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"64K",
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"256K",
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"1M",
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"4M",
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"16M",
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"64M",
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"256M",
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"1G",
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};
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#define INVALID_MASK 0xffffffffLL
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static const uint64_t encmask_2_mask[] = {
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0x0fffLL, /* 4k, 0000 */
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0x3fffLL, /* 16k, 0001 */
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0xffffLL, /* 64k, 0010 */
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0x3ffffLL, /* 256k, 0011 */
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0xfffffLL, /* 1m, 0100 */
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0x3fffffLL, /* 4m, 0101 */
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0xffffffLL, /* 16m, 0110 */
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0x3ffffffLL, /* 64m, 0111 */
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0xfffffffLL, /* 256m, 1000 */
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0x3fffffffLL, /* 1g, 1001 */
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INVALID_MASK, /* RSVD, 1010 */
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};
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static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry)
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{
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if (entry == 0) {
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qemu_log_mask(CPU_LOG_MMU, "%s: Supplied TLB entry was 0!\n",
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__func__);
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return 0;
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}
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tlb_pgsize_t size = ctz64(entry);
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g_assert(size < NUM_PGSIZE_TYPES);
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return size;
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}
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static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry)
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{
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return 1ull << (qemu_target_page_bits() + 2 * hex_tlb_pgsize_type(entry));
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}
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static inline uint64_t hex_tlb_phys_page_num(uint64_t entry)
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{
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uint32_t ppd = GET_PPD(entry);
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return ppd >> 1;
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}
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static inline uint64_t hex_tlb_phys_addr(uint64_t entry)
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{
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uint64_t pagemask = encmask_2_mask[hex_tlb_pgsize_type(entry)];
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uint64_t pagenum = hex_tlb_phys_page_num(entry);
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uint64_t PA = (pagenum << qemu_target_page_bits()) & (~pagemask);
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return PA;
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}
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static inline uint64_t hex_tlb_virt_addr(uint64_t entry)
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{
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return (uint64_t)GET_PTE_VPN(entry) << qemu_target_page_bits();
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}
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bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry)
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{
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if (GET_PTE_V(entry)) {
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uint64_t PA = hex_tlb_phys_addr(entry);
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uint64_t VA = hex_tlb_virt_addr(entry);
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monitor_printf(mon, "0x%016" PRIx64 ": ", entry);
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monitor_printf(mon, "V:%" PRId64 " G:%" PRId64
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" A1:%" PRId64 " A0:%" PRId64,
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GET_PTE_V(entry),
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GET_PTE_G(entry),
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GET_PTE_ATR1(entry),
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GET_PTE_ATR0(entry));
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monitor_printf(mon, " ASID:0x%02" PRIx64 " VA:0x%08" PRIx64,
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GET_PTE_ASID(entry), VA);
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monitor_printf(mon,
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" X:%" PRId64 " W:%" PRId64 " R:%" PRId64
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" U:%" PRId64 " C:%" PRId64,
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GET_PTE_X(entry),
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GET_PTE_W(entry),
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GET_PTE_R(entry),
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GET_PTE_U(entry),
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GET_PTE_C(entry));
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monitor_printf(mon, " PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")",
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PA, pgsize_str[hex_tlb_pgsize_type(entry)],
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hex_tlb_page_size_bytes(entry));
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monitor_printf(mon, "\n");
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return true;
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}
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/* Not valid */
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return false;
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}
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static inline bool hex_tlb_entry_match_noperm(uint64_t entry, uint32_t asid,
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uint64_t VA)
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{
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if (GET_PTE_V(entry)) {
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if (GET_PTE_G(entry)) {
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/* Global entry - ignore ASID */
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} else if (asid != NO_ASID) {
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uint32_t tlb_asid = GET_PTE_ASID(entry);
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if (tlb_asid != asid) {
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return false;
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}
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}
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uint64_t page_size = hex_tlb_page_size_bytes(entry);
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uint64_t page_start =
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ROUND_DOWN(hex_tlb_virt_addr(entry), page_size);
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if (page_start <= VA && VA < page_start + page_size) {
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return true;
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}
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}
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return false;
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}
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static inline void hex_tlb_entry_get_perm(uint64_t entry,
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MMUAccessType access_type,
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int mmu_idx, int *prot,
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int32_t *excp, int *cause_code)
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{
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bool perm_x = GET_PTE_X(entry);
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bool perm_w = GET_PTE_W(entry);
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bool perm_r = GET_PTE_R(entry);
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bool perm_u = GET_PTE_U(entry);
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bool user_idx = mmu_idx == MMU_USER_IDX;
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if (mmu_idx == MMU_KERNEL_IDX) {
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*prot = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return;
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}
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*prot = PAGE_VALID;
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switch (access_type) {
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case MMU_INST_FETCH:
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if (user_idx && !perm_u) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_FETCH_NO_UPAGE;
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} else if (!perm_x) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_FETCH_NO_XPAGE;
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}
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break;
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case MMU_DATA_LOAD:
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if (user_idx && !perm_u) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_PRIV_NO_UREAD;
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} else if (!perm_r) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_PRIV_NO_READ;
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}
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break;
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case MMU_DATA_STORE:
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if (user_idx && !perm_u) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_PRIV_NO_UWRITE;
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} else if (!perm_w) {
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*excp = HEX_EVENT_PRECISE;
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*cause_code = HEX_CAUSE_PRIV_NO_WRITE;
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}
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break;
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}
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if (!user_idx || perm_u) {
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if (perm_x) {
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*prot |= PAGE_EXEC;
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}
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if (perm_r) {
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*prot |= PAGE_READ;
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}
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if (perm_w) {
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*prot |= PAGE_WRITE;
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}
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}
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}
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static inline bool hex_tlb_entry_match(uint64_t entry, uint8_t asid,
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uint32_t VA,
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MMUAccessType access_type, hwaddr *PA,
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int *prot, uint64_t *size,
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int32_t *excp, int *cause_code,
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int mmu_idx)
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{
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if (hex_tlb_entry_match_noperm(entry, asid, VA)) {
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hex_tlb_entry_get_perm(entry, access_type, mmu_idx, prot, excp,
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cause_code);
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*PA = hex_tlb_phys_addr(entry);
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*size = hex_tlb_page_size_bytes(entry);
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return true;
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}
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return false;
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}
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static bool hex_tlb_is_match(uint64_t entry1, uint64_t entry2,
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bool consider_gbit)
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{
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bool valid1 = GET_PTE_V(entry1);
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bool valid2 = GET_PTE_V(entry2);
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uint64_t size1 = hex_tlb_page_size_bytes(entry1);
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uint64_t vaddr1 = ROUND_DOWN(hex_tlb_virt_addr(entry1), size1);
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uint64_t size2 = hex_tlb_page_size_bytes(entry2);
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uint64_t vaddr2 = ROUND_DOWN(hex_tlb_virt_addr(entry2), size2);
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int asid1 = GET_PTE_ASID(entry1);
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int asid2 = GET_PTE_ASID(entry2);
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bool gbit1 = GET_PTE_G(entry1);
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bool gbit2 = GET_PTE_G(entry2);
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if (!valid1 || !valid2) {
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return false;
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}
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if (((vaddr1 <= vaddr2) && (vaddr2 < (vaddr1 + size1))) ||
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((vaddr2 <= vaddr1) && (vaddr1 < (vaddr2 + size2)))) {
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if (asid1 == asid2) {
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return true;
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}
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if ((consider_gbit && gbit1) || gbit2) {
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return true;
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}
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}
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return false;
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}
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/* Public API */
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uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index)
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{
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g_assert(index < tlb->num_entries);
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return tlb->entries[index];
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}
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void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t value)
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{
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g_assert(index < tlb->num_entries);
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tlb->entries[index] = value;
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}
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bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid,
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uint32_t VA, MMUAccessType access_type,
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hwaddr *PA, int *prot, uint64_t *size,
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int32_t *excp, int *cause_code, int mmu_idx)
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{
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*PA = 0;
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*prot = 0;
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*size = 0;
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*excp = 0;
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*cause_code = 0;
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for (uint32_t i = 0; i < tlb->num_entries; i++) {
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if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type,
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PA, prot, size, excp, cause_code, mmu_idx)) {
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return true;
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}
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}
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return false;
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}
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uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid,
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uint32_t VA, int *cause_code)
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{
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uint32_t not_found = 0x80000000;
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uint32_t idx = not_found;
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for (uint32_t i = 0; i < tlb->num_entries; i++) {
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uint64_t entry = tlb->entries[i];
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if (hex_tlb_entry_match_noperm(entry, asid, VA)) {
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if (idx != not_found) {
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*cause_code = HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH;
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break;
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}
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idx = i;
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}
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}
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if (idx == not_found) {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: 0x%" PRIx32 ", 0x%08" PRIx32 " => NOT FOUND\n",
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__func__, asid, VA);
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} else {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: 0x%" PRIx32 ", 0x%08" PRIx32 " => %d\n",
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__func__, asid, VA, idx);
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}
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return idx;
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}
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/*
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* Return codes:
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* 0 or positive index of match
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* -1 multiple matches
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* -2 no match
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*/
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int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry,
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uint64_t index)
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{
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int matches = 0;
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int last_match = 0;
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for (uint32_t i = 0; i < tlb->num_entries; i++) {
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if (hex_tlb_is_match(entry, tlb->entries[i], false)) {
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matches++;
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last_match = i;
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}
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}
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if (matches == 1) {
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return last_match;
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}
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if (matches == 0) {
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return -2;
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}
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return -1;
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}
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void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb)
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{
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for (uint32_t i = 0; i < tlb->num_entries; i++) {
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hexagon_tlb_dump_entry(mon, tlb->entries[i]);
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}
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}
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uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb)
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{
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return tlb->num_entries;
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}
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/* QOM lifecycle */
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static void hexagon_tlb_init(Object *obj)
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{
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}
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static void hexagon_tlb_realize(DeviceState *dev, Error **errp)
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{
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HexagonTLBState *s = HEXAGON_TLB(dev);
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if (s->num_entries == 0 || s->num_entries > MAX_TLB_ENTRIES) {
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error_setg(errp, "Invalid TLB num-entries: %" PRIu32,
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s->num_entries);
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return;
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}
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s->entries = g_new0(uint64_t, s->num_entries);
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}
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static void hexagon_tlb_unrealize(DeviceState *dev)
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{
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HexagonTLBState *s = HEXAGON_TLB(dev);
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g_free(s->entries);
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s->entries = NULL;
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}
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static void hexagon_tlb_reset_hold(Object *obj, ResetType type)
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{
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HexagonTLBState *s = HEXAGON_TLB(obj);
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if (s->entries) {
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memset(s->entries, 0, sizeof(uint64_t) * s->num_entries);
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}
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}
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static const VMStateDescription vmstate_hexagon_tlb = {
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.name = "hexagon-tlb",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(num_entries, HexagonTLBState),
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VMSTATE_VARRAY_UINT32_ALLOC(entries, HexagonTLBState, num_entries,
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0, vmstate_info_uint64, uint64_t),
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VMSTATE_END_OF_LIST()
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},
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};
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static const Property hexagon_tlb_properties[] = {
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DEFINE_PROP_UINT32("num-entries", HexagonTLBState, num_entries,
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MAX_TLB_ENTRIES),
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};
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static void hexagon_tlb_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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dc->realize = hexagon_tlb_realize;
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dc->unrealize = hexagon_tlb_unrealize;
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rc->phases.hold = hexagon_tlb_reset_hold;
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dc->vmsd = &vmstate_hexagon_tlb;
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dc->user_creatable = false;
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device_class_set_props(dc, hexagon_tlb_properties);
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}
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static const TypeInfo hexagon_tlb_info = {
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.name = TYPE_HEXAGON_TLB,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(HexagonTLBState),
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.instance_init = hexagon_tlb_init,
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.class_init = hexagon_tlb_class_init,
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};
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static void hexagon_tlb_register_types(void)
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{
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type_register_static(&hexagon_tlb_info);
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}
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type_init(hexagon_tlb_register_types)
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