Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
/*
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* ASPEED PWM Controller
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*
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* Copyright (C) 2017-2021 IBM Corp.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/misc/aspeed_pwm.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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AspeedPWMState *s = ASPEED_PWM(opaque);
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uint64_t val = 0;
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addr >>= 2;
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if (addr >= ASPEED_PWM_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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} else {
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val = s->regs[addr];
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}
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trace_aspeed_pwm_read(addr << 2, val);
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return val;
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}
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static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedPWMState *s = ASPEED_PWM(opaque);
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trace_aspeed_pwm_write(addr, data);
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addr >>= 2;
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if (addr >= ASPEED_PWM_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return;
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}
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s->regs[addr] = data;
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}
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static const MemoryRegionOps aspeed_pwm_ops = {
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.read = aspeed_pwm_read,
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.write = aspeed_pwm_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void aspeed_pwm_reset_hold(Object *obj, ResetType type)
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{
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AspeedPWMState *s = ASPEED_PWM(obj);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static void aspeed_pwm_realize(DeviceState *dev, Error **errp)
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{
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AspeedPWMState *s = ASPEED_PWM(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s,
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TYPE_ASPEED_PWM, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_pwm = {
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.name = TYPE_ASPEED_PWM,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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dc->realize = aspeed_pwm_realize;
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rc->phases.hold = aspeed_pwm_reset_hold;
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dc->desc = "Aspeed PWM Controller";
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dc->vmsd = &vmstate_aspeed_pwm;
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}
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static const TypeInfo aspeed_pwm_types[] = {
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{
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.name = TYPE_ASPEED_PWM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedPWMState),
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.class_init = aspeed_pwm_class_init,
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}
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};
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DEFINE_TYPES(aspeed_pwm_types)
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