Yaya48
5d9a60a926
Model the A6 crypto, interrupt, USB, and platform blocks needed to boot SecureROM through iBSS into iBEC Recovery. Add local lab identity, IMG3, and APTicket tooling, patched macOS recovery utilities, UART and GDB access, and English end-user documentation.
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
/*
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* Apple S5L8950X DRAM controller training/status model.
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*
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* iBEC programs the timing registers and then waits for the controller and
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* PHY training state in register zero. QEMU's RAM is already usable, so the
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* training phases complete synchronously while ordinary register values are
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* retained for debugger inspection.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/arm/s5l8950x.h"
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#include "hw/core/sysbus.h"
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#include "qom/object.h"
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#define S5L8950X_MEMCTL_REGION_SIZE 0x1000
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#define S5L8950X_MEMCTL_NUM_REGS \
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(S5L8950X_MEMCTL_REGION_SIZE / sizeof(uint32_t))
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/* Controller ready, PHY ready and all low training stages complete. */
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#define S5L8950X_MEMCTL_READY 0x801003ffu
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OBJECT_DECLARE_SIMPLE_TYPE(S5L8950XMemctlState, S5L8950X_MEMCTL)
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struct S5L8950XMemctlState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[S5L8950X_MEMCTL_NUM_REGS];
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};
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static uint64_t s5l8950x_memctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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S5L8950XMemctlState *s = opaque;
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if (offset == 0) {
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uint32_t status = s->regs[0] | S5L8950X_MEMCTL_READY;
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/*
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* The 0b101 command starts a training phase whose lane bits are
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* active-low. iBEC clears the command before waiting for them to
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* return to the completed state.
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*/
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if ((s->regs[0x14 / 4] & 5) == 5) {
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status &= ~0x000003f0u;
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}
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/*
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* Register 0x08 bit 31 requests a controller state transition. The
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* corresponding completion state is exposed in status bit 10 and is
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* cleared again when iBEC drops the request.
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*/
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if (s->regs[0x08 / 4] & BIT(31)) {
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status |= BIT(10);
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} else {
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status &= ~BIT(10);
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}
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return status;
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}
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/*
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* The PHY command/status block starts at 0x34. Its status register at
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* 0x44 reports both command-complete stages once the programmed timing
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* values have been accepted.
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*/
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if (offset == 0x44) {
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return s->regs[offset / sizeof(uint32_t)] | 0x00500000u;
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}
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return s->regs[offset / sizeof(uint32_t)];
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}
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static void s5l8950x_memctl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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S5L8950XMemctlState *s = opaque;
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s->regs[offset / sizeof(uint32_t)] = value;
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}
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static const MemoryRegionOps s5l8950x_memctl_ops = {
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.read = s5l8950x_memctl_read,
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.write = s5l8950x_memctl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void s5l8950x_memctl_reset(DeviceState *dev)
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{
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S5L8950XMemctlState *s = S5L8950X_MEMCTL(dev);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static void s5l8950x_memctl_init(Object *obj)
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{
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S5L8950XMemctlState *s = S5L8950X_MEMCTL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &s5l8950x_memctl_ops, s,
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TYPE_S5L8950X_MEMCTL,
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S5L8950X_MEMCTL_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void s5l8950x_memctl_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, s5l8950x_memctl_reset);
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}
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static const TypeInfo s5l8950x_memctl_info = {
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.name = TYPE_S5L8950X_MEMCTL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(S5L8950XMemctlState),
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.instance_init = s5l8950x_memctl_init,
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.class_init = s5l8950x_memctl_class_init,
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};
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static void s5l8950x_memctl_register_types(void)
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{
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type_register_static(&s5l8950x_memctl_info);
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}
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type_init(s5l8950x_memctl_register_types)
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