Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
25 lines
1.4 KiB
Meson
25 lines
1.4 KiB
Meson
riscv_ss = ss.source_set()
|
|
riscv_ss.add(files('aia.c'))
|
|
riscv_ss.add(files('boot.c'))
|
|
riscv_ss.add(files('fdt-common.c'))
|
|
riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
|
|
riscv_ss.add(files('riscv_hart.c'))
|
|
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
|
|
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
|
|
riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
|
|
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
|
|
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
|
|
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
|
|
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
|
|
riscv_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis.c'))
|
|
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
|
|
riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
|
|
'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
|
|
riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
|
|
riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))
|
|
riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
|
|
riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
|
|
riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c'))
|
|
|
|
hw_arch += {'riscv': riscv_ss}
|