Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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*
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* Copyright (c) 2015 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Define macros useful when building ARM device tree nodes
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*/
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#ifndef QEMU_ARM_FDT_H
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#define QEMU_ARM_FDT_H
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/*
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* These are for GICv2/v3/v4 only; GICv5 encodes the interrupt type in
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* the DTB "interrupts" properties differently, using constants that
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* match the architectural INTID.Type. In QEMU those are available as
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* the GICV5_PPI and GICV5_SPI enum values in arm_gicv5_types.h.
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*/
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#define GIC_FDT_IRQ_TYPE_SPI 0
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#define GIC_FDT_IRQ_TYPE_PPI 1
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/*
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* The trigger type/level field in the DTB "interrupts" property has
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* the same encoding for GICv2/v3/v4 and v5.
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*/
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#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
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#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
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#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
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#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
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#define GIC_FDT_IRQ_PPI_CPU_START 8
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#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
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#endif
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