Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
270 lines
7.4 KiB
C
270 lines
7.4 KiB
C
/*
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* QEMU CXL Events
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*
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* Copyright (c) 2022 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_EVENTS_H
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#define CXL_EVENTS_H
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#include "qemu/uuid.h"
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/*
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* CXL r3.1 section 8.2.9.2.2: Get Event Records (Opcode 0100h); Table 8-52
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*
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* Define these as the bit position for the event status register for ease of
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* setting the status.
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*/
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typedef enum CXLEventLogType {
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CXL_EVENT_TYPE_INFO = 0,
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CXL_EVENT_TYPE_WARN = 1,
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CXL_EVENT_TYPE_FAIL = 2,
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CXL_EVENT_TYPE_FATAL = 3,
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CXL_EVENT_TYPE_DYNAMIC_CAP = 4,
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CXL_EVENT_TYPE_MAX
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} CXLEventLogType;
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/*
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* Common Event Record Format
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* CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
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*/
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#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
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#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
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#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
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#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
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#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
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#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
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#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
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typedef struct CXLEventRecordHdr {
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QemuUUID id;
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uint8_t length;
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uint8_t flags[3];
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uint16_t handle;
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uint16_t related_handle;
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uint64_t timestamp;
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uint8_t maint_op_class;
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uint8_t maint_op_subclass;
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uint16_t ld_id;
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uint8_t head_id;
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uint8_t reserved[0xb];
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} QEMU_PACKED CXLEventRecordHdr;
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#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
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typedef struct CXLEventRecordRaw {
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CXLEventRecordHdr hdr;
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uint8_t data[CXL_EVENT_RECORD_DATA_LENGTH];
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} QEMU_PACKED CXLEventRecordRaw;
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#define CXL_EVENT_RECORD_SIZE (sizeof(CXLEventRecordRaw))
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/*
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* Get Event Records output payload
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* CXL r3.1 section 8.2.9.2.2; Table 8-53
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*/
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#define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
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#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
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typedef struct CXLGetEventPayload {
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uint8_t flags;
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uint8_t reserved1;
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uint16_t overflow_err_count;
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uint64_t first_overflow_timestamp;
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uint64_t last_overflow_timestamp;
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uint16_t record_count;
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uint8_t reserved2[0xa];
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CXLEventRecordRaw records[];
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} QEMU_PACKED CXLGetEventPayload;
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#define CXL_EVENT_PAYLOAD_HDR_SIZE (sizeof(CXLGetEventPayload))
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/*
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* Clear Event Records input payload
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* CXL r3.1 section 8.2.9.2.3; Table 8-54
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*/
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typedef struct CXLClearEventPayload {
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uint8_t event_log; /* CXLEventLogType */
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uint8_t clear_flags;
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uint8_t nr_recs;
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uint8_t reserved[3];
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uint16_t handle[];
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} CXLClearEventPayload;
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/*
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* Event Interrupt Policy
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*
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* CXL r3.1 section 8.2.9.2.4; Table 8-55
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*/
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typedef enum CXLEventIntMode {
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CXL_INT_NONE = 0x00,
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CXL_INT_MSI_MSIX = 0x01,
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CXL_INT_FW = 0x02,
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CXL_INT_RES = 0x03,
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} CXLEventIntMode;
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#define CXL_EVENT_INT_MODE_MASK 0x3
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#define CXL_EVENT_INT_SETTING(vector) \
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((((uint8_t)vector & 0xf) << 4) | CXL_INT_MSI_MSIX)
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typedef struct CXLEventInterruptPolicy {
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uint8_t info_settings;
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uint8_t warn_settings;
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uint8_t failure_settings;
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uint8_t fatal_settings;
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uint8_t dyn_cap_settings;
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} QEMU_PACKED CXLEventInterruptPolicy;
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/* DCD is optional but other fields are not */
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#define CXL_EVENT_INT_SETTING_MIN_LEN 4
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/*
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* General Media Event Record
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* CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
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*/
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#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
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#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
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typedef struct CXLEventGenMedia {
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CXLEventRecordHdr hdr;
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uint64_t phys_addr;
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uint8_t descriptor;
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uint8_t type;
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uint8_t transaction_type;
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uint16_t validity_flags;
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uint8_t channel;
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uint8_t rank;
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uint8_t device[3];
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uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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uint8_t cme_ev_flags;
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uint8_t cme_count[3];
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uint8_t sub_type;
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uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
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} QEMU_PACKED CXLEventGenMedia;
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/*
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* DRAM Event Record
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* CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
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* All fields little endian.
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*/
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typedef struct CXLEventDram {
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CXLEventRecordHdr hdr;
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uint64_t phys_addr;
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uint8_t descriptor;
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uint8_t type;
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uint8_t transaction_type;
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uint16_t validity_flags;
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uint8_t channel;
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uint8_t rank;
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uint8_t nibble_mask[3];
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uint8_t bank_group;
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uint8_t bank;
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uint8_t row[3];
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uint16_t column;
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uint64_t correction_mask[4];
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uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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uint8_t sub_channel;
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uint8_t cme_ev_flags;
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uint8_t cvme_count[3];
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uint8_t sub_type;
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uint8_t reserved;
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} QEMU_PACKED CXLEventDram;
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/*
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* Memory Module Event Record
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* CXL r3.2 Section 8.2.10.2.1.3: Table 8-59
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* All fields little endian.
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*/
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typedef struct CXLEventMemoryModule {
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CXLEventRecordHdr hdr;
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uint8_t type;
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uint8_t health_status;
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uint8_t media_status;
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uint8_t additional_status;
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uint8_t life_used;
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int16_t temperature;
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uint32_t dirty_shutdown_count;
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uint32_t corrected_volatile_error_count;
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uint32_t corrected_persistent_error_count;
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uint16_t validity_flags;
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uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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uint8_t sub_type;
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uint8_t reserved[0x2a];
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} QEMU_PACKED CXLEventMemoryModule;
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/*
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* CXL r3.1 section Table 8-50: Dynamic Capacity Event Record
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* All fields little endian.
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*/
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typedef struct CXLEventDynamicCapacity {
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CXLEventRecordHdr hdr;
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uint8_t type;
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uint8_t validity_flags;
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uint16_t host_id;
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uint8_t updated_region_id;
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uint8_t flags;
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uint8_t reserved2[2];
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uint8_t dynamic_capacity_extent[0x28]; /* defined in cxl_device.h */
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uint8_t reserved[0x18];
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uint32_t extents_avail;
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uint32_t tags_avail;
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} QEMU_PACKED CXLEventDynamicCapacity;
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/* CXL r3.1 Table 8-50: Dynamic Capacity Event Record */
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static const QemuUUID dynamic_capacity_uuid = {
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.data = UUID(0xca95afa7, 0xf183, 0x4018, 0x8c, 0x2f,
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0x95, 0x26, 0x8e, 0x10, 0x1a, 0x2a),
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};
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typedef enum CXLDCEventType {
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DC_EVENT_ADD_CAPACITY = 0x0,
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DC_EVENT_RELEASE_CAPACITY = 0x1,
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DC_EVENT_FORCED_RELEASE_CAPACITY = 0x2,
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DC_EVENT_REGION_CONFIG_UPDATED = 0x3,
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DC_EVENT_ADD_CAPACITY_RSP = 0x4,
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DC_EVENT_CAPACITY_RELEASED = 0x5,
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} CXLDCEventType;
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/*
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* CXL r3.2 section Table 8-60: Memory Sparing Event Record
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* All fields little endian.
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*/
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#define CXL_MSER_FLAGS_QUERY_RESOURCES BIT(0)
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#define CXL_MSER_FLAGS_HARD_SPARING BIT(1)
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#define CXL_MSER_FLAGS_DEV_INITIATED BIT(2)
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#define CXL_MSER_VALID_CHANNEL BIT(0)
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#define CXL_MSER_VALID_RANK BIT(1)
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#define CXL_MSER_VALID_NIB_MASK BIT(2)
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#define CXL_MSER_VALID_BANK_GROUP BIT(3)
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#define CXL_MSER_VALID_BANK BIT(4)
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#define CXL_MSER_VALID_ROW BIT(5)
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#define CXL_MSER_VALID_COLUMN BIT(6)
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#define CXL_MSER_VALID_COMP_ID BIT(7)
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#define CXL_MSER_VALID_COMP_ID_FORMAT BIT(8)
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#define CXL_MSER_VALID_SUB_CHANNEL BIT(9)
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typedef struct CXLEventSparing {
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CXLEventRecordHdr hdr;
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uint8_t maint_op_class;
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uint8_t maint_op_subclass;
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uint8_t flags;
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uint8_t result;
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uint16_t validity_flags;
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uint8_t reserved1[6];
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uint16_t res_avail;
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uint8_t channel;
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uint8_t rank;
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uint8_t nibble_mask[3];
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uint8_t bank_group;
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uint8_t bank;
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uint8_t row[3];
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uint16_t column;
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uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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uint8_t sub_channel;
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uint8_t reserved2[0x25];
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} QEMU_PACKED CXLEventSparing;
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/* CXL r3.2 Table 8-60: Memory Sparing Event Record */
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static const QemuUUID sparing_uuid = {
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.data = UUID(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39,
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0x4d, 0x1c, 0x96, 0x6c, 0x7c, 0x65),
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};
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#endif /* CXL_EVENTS_H */
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