Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* Hexagon Global Registers QOM Object
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*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HEXAGON_GLOBALREG_H
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#define HEXAGON_GLOBALREG_H
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#include "hw/core/qdev.h"
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#include "hw/core/sysbus.h"
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#include "hw/intc/hex-l2vic.h"
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#include "hw/timer/qct-qtimer.h"
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#include "qom/object.h"
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#include "target/hexagon/cpu.h"
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#define TYPE_HEXAGON_GLOBALREG "hexagon-globalreg"
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OBJECT_DECLARE_SIMPLE_TYPE(HexagonGlobalRegState, HEXAGON_GLOBALREG)
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struct HexagonGlobalRegState {
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SysBusDevice parent_obj;
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/* Array of system registers */
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uint32_t regs[NUM_SREGS];
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/* L2VIC interface used to back the VID/VID1 registers */
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HexL2VicInterface *l2vic;
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/* QTimer interface used to back the TIMERLO/TIMERHI registers */
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QctQtimerInterface *qtimer;
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/* Global performance cycle counter base */
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uint64_t g_pcycle_base;
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/* Properties for global register reset values */
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uint32_t boot_evb; /* Boot Exception Vector Base (HEX_SREG_EVB) */
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uint64_t config_table_addr; /* Configuration table base */
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uint32_t dsp_rev; /* DSP revision register (HEX_SREG_REV) */
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/* ISDB properties */
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bool isdben_etm_enable; /* ISDB ETM enable bit */
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bool isdben_dfd_enable; /* ISDB DFD enable bit */
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bool isdben_trusted; /* ISDB trusted mode bit */
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bool isdben_secure; /* ISDB secure mode bit */
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};
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/* Public interface functions */
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uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t htid);
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void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value, uint32_t htid);
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uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value);
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void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value);
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/* Global performance cycle counter access */
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uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s);
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void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s,
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uint64_t value);
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#endif /* HEXAGON_GLOBALREG_H */
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