Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
88 lines
3.0 KiB
C
88 lines
3.0 KiB
C
/*
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* A test device for IOMMU
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*
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* Copyright (c) 2026 Phytium Technology
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*
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* Author:
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* Tao Tang <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MISC_IOMMU_TESTDEV_H
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#define HW_MISC_IOMMU_TESTDEV_H
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#include "hw/pci/pci.h"
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#define IOMMU_TESTDEV_VENDOR_ID PCI_VENDOR_ID_REDHAT
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#define IOMMU_TESTDEV_DEVICE_ID PCI_DEVICE_ID_REDHAT_TEST
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/* DMA_ATTRS register bit definitions which shadow some fields in MemTxAttrs */
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#define ITD_ATTRS_SECURE_SHIFT 0
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#define ITD_ATTRS_SECURE_MASK 0x1
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#define ITD_ATTRS_SPACE_SHIFT 1
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#define ITD_ATTRS_SPACE_MASK 0x3
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#define ITD_ATTRS_SPACE_VALID_SHIFT 3
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#define ITD_ATTRS_SPACE_VALID_MASK 0x1
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#define ITD_ATTRS_SPACE_SECURE 0
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#define ITD_ATTRS_SPACE_NONSECURE 1
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/* Helper macros for setting fields */
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#define ITD_ATTRS_SET_SECURE(attrs, val) \
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(((attrs) & ~(ITD_ATTRS_SECURE_MASK << ITD_ATTRS_SECURE_SHIFT)) | \
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(((val) & ITD_ATTRS_SECURE_MASK) << ITD_ATTRS_SECURE_SHIFT))
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#define ITD_ATTRS_SET_SPACE(attrs, val) \
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(((attrs) & ~(ITD_ATTRS_SPACE_MASK << ITD_ATTRS_SPACE_SHIFT)) | \
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(((val) & ITD_ATTRS_SPACE_MASK) << ITD_ATTRS_SPACE_SHIFT))
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#define ITD_ATTRS_SET_SPACE_VALID(attrs, val) \
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(((attrs) & ~(ITD_ATTRS_SPACE_VALID_MASK << \
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ITD_ATTRS_SPACE_VALID_SHIFT)) | \
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(((val) & ITD_ATTRS_SPACE_VALID_MASK) << \
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ITD_ATTRS_SPACE_VALID_SHIFT))
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/* Helper macros for getting fields */
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#define ITD_ATTRS_GET_SECURE(attrs) \
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(((attrs) >> ITD_ATTRS_SECURE_SHIFT) & ITD_ATTRS_SECURE_MASK)
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#define ITD_ATTRS_GET_SPACE(attrs) \
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(((attrs) >> ITD_ATTRS_SPACE_SHIFT) & ITD_ATTRS_SPACE_MASK)
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#define ITD_ATTRS_GET_SPACE_VALID(attrs) \
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(((attrs) >> ITD_ATTRS_SPACE_VALID_SHIFT) & \
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ITD_ATTRS_SPACE_VALID_MASK)
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/* DMA result/status values shared with tests */
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#define ITD_DMA_RESULT_IDLE 0xffffffffu
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#define ITD_DMA_RESULT_BUSY 0xfffffffeu
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#define ITD_DMA_ERR_BAD_LEN 0xdead0001u
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#define ITD_DMA_ERR_TX_FAIL 0xdead0002u
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#define ITD_DMA_ERR_RD_FAIL 0xdead0003u
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#define ITD_DMA_ERR_MISMATCH 0xdead0004u
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#define ITD_DMA_ERR_NOT_ARMED 0xdead0005u
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#define ITD_DMA_ERR_BAD_ATTRS 0xdead0006u
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#define ITD_DMA_WRITE_VAL 0x12345678u
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/* DMA doorbell bits */
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#define ITD_DMA_DBELL_ARM 0x1u
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/* BAR0 layout of iommu-testdev */
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enum {
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ITD_REG_DMA_TRIGGERING = 0x00,
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ITD_REG_DMA_GVA_LO = 0x04,
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ITD_REG_DMA_GVA_HI = 0x08,
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ITD_REG_DMA_LEN = 0x0c,
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ITD_REG_DMA_RESULT = 0x10,
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ITD_REG_DMA_DBELL = 0x14,
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/* [0] secure,[2:1] ArmSecuritySpace,[3] space_valid */
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ITD_REG_DMA_ATTRS = 0x18,
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ITD_REG_DMA_GPA_LO = 0x1c,
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ITD_REG_DMA_GPA_HI = 0x20,
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BAR0_SIZE = 0x1000,
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};
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#endif /* HW_MISC_IOMMU_TESTDEV_H */
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