Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/*
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* sPAPR CPU core device.
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*
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* Copyright (C) 2016 Bharata B Rao <[email protected]>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_CPU_CORE_H
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#define HW_SPAPR_CPU_CORE_H
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#include "hw/cpu/core.h"
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#include "hw/core/qdev.h"
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#include "target/ppc/cpu-qom.h"
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#include "target/ppc/cpu.h"
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#include "qom/object.h"
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#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
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OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
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SPAPR_CPU_CORE)
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#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
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struct SpaprCpuCore {
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/*< private >*/
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CPUCore parent_obj;
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/*< public >*/
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PowerPCCPU **threads;
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int node_id;
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};
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struct SpaprCpuCoreClass {
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DeviceClass parent_class;
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const char *cpu_type;
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};
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const char *spapr_get_cpu_core_type(const char *cpu_type);
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
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target_ulong r1, target_ulong r3,
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target_ulong r4);
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struct nested_ppc_state;
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typedef struct SpaprCpuState {
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uint64_t vpa_addr;
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uint64_t slb_shadow_addr, slb_shadow_size;
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uint64_t dtl_addr, dtl_size;
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bool prod; /* not migrated, only used to improve dispatch latencies */
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struct ICPState *icp;
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struct XiveTCTX *tctx;
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/* Fields for nested-HV support */
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bool in_nested; /* true while the L2 is executing */
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struct nested_ppc_state *nested_host_state; /* holds the L1 state while L2 executes */
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} SpaprCpuState;
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static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
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{
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return (SpaprCpuState *)cpu->machine_data;
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}
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#endif
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