Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
159 lines
3.6 KiB
C
159 lines
3.6 KiB
C
/*
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* QEMU RISC-V Virt Board Compatible with kendryte K230 SDK
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*
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* Copyright (c) 2025 Chao Liu <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Provides a board compatible with the kendryte K230 SDK
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*
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* K230 Technical Reference Manual V0.3.1 (2024-11-18):
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* https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
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*
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* For more information, see <https://www.kendryte.com/en/proDetail/230>
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*/
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#ifndef HW_K230_H
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#define HW_K230_H
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#include "hw/core/boards.h"
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#include "hw/misc/k230_ddr.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/watchdog/k230_wdt.h"
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#include "hw/dma/k230_gsdma.h"
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#include "hw/misc/k230_decomp_gzip.h"
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#define C908_CPU_HARTID (0)
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#define TYPE_RISCV_K230_SOC "riscv.k230.soc"
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#define RISCV_K230_SOC(obj) \
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OBJECT_CHECK(K230SoCState, (obj), TYPE_RISCV_K230_SOC)
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typedef struct K230SoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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RISCVHartArrayState c908_cpu; /* Small core */
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K230DDRCfgState ddr_cfg;
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K230DDRPhyState ddr_phy;
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K230WdtState wdt[2];
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K230GSDMAState gsdma;
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K230DecompGzipState decomp_gzip;
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MemoryRegion sram;
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MemoryRegion bootrom;
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DeviceState *c908_plic;
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} K230SoCState;
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#define TYPE_RISCV_K230_MACHINE MACHINE_TYPE_NAME("k230")
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#define RISCV_K230_MACHINE(obj) \
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OBJECT_CHECK(K230MachineState, (obj), TYPE_RISCV_K230_MACHINE)
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typedef struct K230MachineState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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K230SoCState soc;
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Notifier machine_done;
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} K230MachineState;
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enum {
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K230_DEV_DDRC,
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K230_DEV_KPU_L2_CACHE,
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K230_DEV_SRAM,
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K230_DEV_KPU_CFG,
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K230_DEV_FFT,
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K230_DEV_AI_2D_ENGINE,
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K230_DEV_GSDMA,
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K230_DEV_DMA,
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K230_DEV_DECOMP_GZIP,
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K230_DEV_NON_AI_2D,
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K230_DEV_ISP,
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K230_DEV_DEWARP,
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K230_DEV_RX_CSI,
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K230_DEV_H264,
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K230_DEV_2P5D,
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K230_DEV_VO,
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K230_DEV_VO_CFG,
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K230_DEV_3D_ENGINE,
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K230_DEV_PMU,
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K230_DEV_RTC,
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K230_DEV_CMU,
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K230_DEV_RMU,
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K230_DEV_BOOT,
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K230_DEV_PWR,
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K230_DEV_MAILBOX,
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K230_DEV_IOMUX,
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K230_DEV_TIMER,
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K230_DEV_WDT0,
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K230_DEV_WDT1,
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K230_DEV_TS,
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K230_DEV_HDI,
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K230_DEV_STC,
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K230_DEV_BOOTROM,
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K230_DEV_SECURITY,
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K230_DEV_UART0,
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K230_DEV_UART1,
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K230_DEV_UART2,
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K230_DEV_UART3,
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K230_DEV_UART4,
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K230_DEV_I2C0,
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K230_DEV_I2C1,
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K230_DEV_I2C2,
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K230_DEV_I2C3,
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K230_DEV_I2C4,
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K230_DEV_PWM,
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K230_DEV_GPIO0,
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K230_DEV_GPIO1,
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K230_DEV_ADC,
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K230_DEV_CODEC,
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K230_DEV_I2S,
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K230_DEV_USB0,
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K230_DEV_USB1,
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K230_DEV_SD0,
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K230_DEV_SD1,
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K230_DEV_QSPI0,
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K230_DEV_QSPI1,
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K230_DEV_SPI,
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K230_DEV_HI_SYS_CFG,
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K230_DEV_DDRC_CFG,
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K230_DEV_DDR_PHY,
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K230_DEV_FLASH,
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K230_DEV_PLIC,
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K230_DEV_CLINT,
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};
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enum {
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/*
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* K230 TRM v0.3.1 section 2.4 lists peripheral interrupt bits; SDK
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* DTBs expose the corresponding PLIC IDs as bit + 16.
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*/
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K230_UART0_IRQ = 16,
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K230_UART1_IRQ = 17,
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K230_UART2_IRQ = 18,
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K230_UART3_IRQ = 19,
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K230_UART4_IRQ = 20,
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K230_WDT0_IRQ = 107,
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K230_WDT1_IRQ = 108,
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K230_GSDMA_IRQ = 140,
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};
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#define K230_UART_COUNT 5
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/*
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* Integrates with the interrupt controller (PLIC),
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* which can process 208 interrupt external sources
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*/
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#define K230_PLIC_NUM_SOURCES 208
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#define K230_PLIC_NUM_PRIORITIES 7
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#define K230_PLIC_PRIORITY_BASE 0x00
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#define K230_PLIC_PENDING_BASE 0x1000
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#define K230_PLIC_ENABLE_BASE 0x2000
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#define K230_PLIC_ENABLE_STRIDE 0x80
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#define K230_PLIC_CONTEXT_BASE 0x200000
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#define K230_PLIC_CONTEXT_STRIDE 0x1000
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#endif
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