Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/*
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* QOM type definitions for riscv32 / riscv64 machines
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*
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* Copyright (c) rev.ng Labs Srl.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_RISCV_MACHINES_QOM_H
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#define HW_RISCV_MACHINES_QOM_H
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#include "hw/core/boards.h"
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#define TYPE_TARGET_RISCV32_MACHINE \
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"target-info-riscv32-machine"
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#define TYPE_TARGET_RISCV64_MACHINE \
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"target-info-riscv64-machine"
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/*
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* Interfaces specifying whether a given QOM object is available in
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* qemu-system-riscv32, qemu-system-riscv64, or both.
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*/
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extern const InterfaceInfo riscv32_machine_interfaces[];
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extern const InterfaceInfo riscv64_machine_interfaces[];
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extern const InterfaceInfo riscv32_64_machine_interfaces[];
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/*
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* Helper macros for defining machines available in qemu-system-riscv32,
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* qemu-system-riscv64, or both.
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*/
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#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
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DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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riscv32_machine_interfaces)
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#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
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DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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riscv64_machine_interfaces)
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#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
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DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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riscv32_64_machine_interfaces)
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#endif
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