Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
65 lines
1.2 KiB
C
65 lines
1.2 KiB
C
/*
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* Tenstorrent Atlantis RISC-V System on Chip
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright 2025 Tenstorrent, Joel Stanley <[email protected]>
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*/
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#ifndef HW_RISCV_TT_ATLANTIS_H
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#define HW_RISCV_TT_ATLANTIS_H
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#include "hw/core/boards.h"
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#include "hw/core/sysbus.h"
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#include "hw/i2c/designware_i2c.h"
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#include "hw/intc/riscv_imsic.h"
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#include "hw/riscv/riscv_hart.h"
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#define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis")
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OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)
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#define TT_ATL_NUM_I2C 5
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struct TTAtlantisState {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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Notifier machine_done;
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const MemMapEntry *memmap;
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RISCVHartArrayState soc;
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DeviceState *irqchip;
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DesignWareI2CState i2c[TT_ATL_NUM_I2C];
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int fdt_size;
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};
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enum {
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TT_ATL_I2C0_IRQ = 33,
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TT_ATL_I2C1_IRQ = 34,
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TT_ATL_I2C2_IRQ = 35,
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TT_ATL_I2C3_IRQ = 36,
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TT_ATL_I2C4_IRQ = 37,
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TT_ATL_UART1_IRQ = 39,
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};
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enum {
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TT_ATL_ACLINT,
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TT_ATL_BOOTROM,
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TT_ATL_DDR_LO,
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TT_ATL_DDR_HI,
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TT_ATL_I2C0,
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TT_ATL_I2C1,
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TT_ATL_I2C2,
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TT_ATL_I2C3,
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TT_ATL_I2C4,
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TT_ATL_MAPLIC,
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TT_ATL_MIMSIC,
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TT_ATL_SAPLIC,
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TT_ATL_SIMSIC,
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TT_ATL_UART1,
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};
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#endif
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