Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* QEMU PowerPC SPI model
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This model Supports a connection to a single SPI responder.
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* Introduced for P10 to provide access to SPI seeproms, TPM, flash device
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* and an ADC controller.
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*
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* All SPI function control is mapped into the SPI register space to enable
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* full control by firmware.
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*
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* SPI Controller has sequencer and shift engine. The SPI shift engine
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* performs serialization and de-serialization according to the control by
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* the sequencer and according to the setup defined in the configuration
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* registers and the SPI sequencer implements the main control logic.
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*/
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#ifndef PPC_PNV_SPI_H
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#define PPC_PNV_SPI_H
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#include "hw/ssi/ssi.h"
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#include "hw/core/sysbus.h"
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#include "qemu/fifo8.h"
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#define TYPE_PNV_SPI "pnv-spi"
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OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI)
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#define PNV_SPI_REG_SIZE 8
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#define PNV_SPI_REGS 7
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#define TYPE_PNV_SPI_BUS "spi"
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typedef struct PnvSpi {
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SysBusDevice parent_obj;
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SSIBus *ssi_bus;
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qemu_irq *cs_line;
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MemoryRegion xscom_spic_regs;
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Fifo8 tx_fifo;
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Fifo8 rx_fifo;
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uint8_t fail_count; /* RDR Match failure counter */
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/* SPI object number */
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uint32_t spic_num;
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uint32_t chip_id;
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uint8_t transfer_len;
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uint8_t responder_select;
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/* To verify if shift_n1 happens prior to shift_n2 */
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bool shift_n1_done;
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/* Loop counter for branch operation opcode Ex/Fx */
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uint8_t loop_counter_1;
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uint8_t loop_counter_2;
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/* N1/N2_bits specifies the size of the N1/N2 segment of a frame in bits.*/
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uint8_t N1_bits;
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uint8_t N2_bits;
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/* Number of bytes in a payload for the N1/N2 frame segment.*/
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uint8_t N1_bytes;
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uint8_t N2_bytes;
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/* Number of N1/N2 bytes marked for transmit */
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uint8_t N1_tx;
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uint8_t N2_tx;
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/* Number of N1/N2 bytes marked for receive */
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uint8_t N1_rx;
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uint8_t N2_rx;
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/* SPI registers */
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uint64_t regs[PNV_SPI_REGS];
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uint8_t seq_op[PNV_SPI_REG_SIZE];
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uint64_t status;
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} PnvSpi;
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#endif /* PPC_PNV_SPI_H */
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