Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/*
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* Xilinx Zynq cadence TTC model
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*
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* Copyright (c) 2011 Xilinx Inc.
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* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written By Haibing Ma
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* M. Habib
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_TIMER_CADENCE_TTC_H
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#define HW_TIMER_CADENCE_TTC_H
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#include "hw/core/sysbus.h"
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#include "qemu/timer.h"
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typedef struct {
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QEMUTimer *timer;
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int freq;
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uint32_t reg_clock;
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uint32_t reg_count;
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uint32_t reg_value;
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uint16_t reg_interval;
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uint16_t reg_match[3];
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uint32_t reg_intr;
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uint32_t reg_intr_en;
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uint32_t reg_event_ctrl;
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uint32_t reg_event;
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uint64_t cpu_time;
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unsigned int cpu_time_valid;
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qemu_irq irq;
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} CadenceTimerState;
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#define TYPE_CADENCE_TTC "cadence_ttc"
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OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
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struct CadenceTTCState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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CadenceTimerState timer[3];
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};
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#endif
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