Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* ARM MemTag convenience functions.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "mte_user_helper.h"
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void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value)
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{
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/*
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* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
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*
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* The kernel has a per-cpu configuration for the sysadmin,
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* /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
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* which qemu does not implement.
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*
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* Because there is no performance difference between the modes, and
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* because SYNC is most useful for debugging MTE errors, choose SYNC
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* as the preferred mode. With this preference, and the way the API
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* uses only two bits, there is no way for the program to select
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* ASYMM mode.
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*/
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unsigned tcf = 0;
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if (value & PR_MTE_TCF_SYNC) {
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tcf = 1;
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} else if (value & PR_MTE_TCF_ASYNC) {
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tcf = 2;
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}
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env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
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/*
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* If MTE_STORE_ONLY is enabled, set the corresponding sctlr_el1 bit
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*/
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if (value & PR_MTE_STORE_ONLY) {
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env->cp15.sctlr_el[1] |= SCTLR_TCSO0;
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} else {
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env->cp15.sctlr_el[1] &= ~SCTLR_TCSO0;
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}
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}
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