Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
42 lines
1.0 KiB
C
42 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "loader.h"
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#include "target_elf.h"
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const char *get_elf_cpu_model(uint32_t eflags)
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{
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return "max";
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}
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void elf_core_copy_fpregs(target_elf_fpregset_t *r, const CPURISCVState *env)
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{
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for (int i = 0; i < 32; i++) {
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r->fpr[i] = tswap64(env->fpr[i]);
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}
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r->fcsr = tswap32(((uint32_t)env->frm << FSR_RD_SHIFT) |
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(riscv_cpu_get_fflags((CPURISCVState *)env) << FSR_AEXC_SHIFT));
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}
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void elf_core_copy_regs(target_elf_gregset_t *r, const CPURISCVState *env)
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{
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r->pc = tswapal(env->pc);
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for (int i = 0; i < 31; i++) {
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r->regs[i] = tswapal(env->gpr[i + 1]);
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}
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}
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abi_ulong get_elf_hwcap(CPUState *cs)
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{
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#define MISA_BIT(EXT) (1 << (EXT - 'A'))
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RISCVCPU *cpu = RISCV_CPU(cs);
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uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
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| MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
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| MISA_BIT('V');
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return cpu->env.misa_ext & mask;
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#undef MISA_BIT
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}
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