Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
59 lines
1.2 KiB
C
59 lines
1.2 KiB
C
/*
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* Target-specific parts of semihosting/arm-compat-semi.c.
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*
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* Copyright (c) 2005, 2007 CodeSourcery.
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* Copyright (c) 2019, 2022 Linaro
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "semihosting/common-semi.h"
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#include "target/arm/cpu-qom.h"
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uint64_t common_semi_arg(CPUState *cs, int argno)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (is_a64(env)) {
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return env->xregs[argno];
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} else {
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return env->regs[argno];
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}
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}
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void common_semi_set_ret(CPUState *cs, uint64_t ret)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (is_a64(env)) {
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env->xregs[0] = ret;
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} else {
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env->regs[0] = ret;
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}
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}
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bool common_semi_sys_exit_is_extended(CPUState *cs)
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{
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return is_a64(cpu_env(cs));
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}
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bool is_64bit_semihosting(CPUArchState *env)
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{
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return is_a64(env);
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}
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uint64_t common_semi_stack_bottom(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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return is_a64(env) ? env->xregs[31] : env->regs[13];
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}
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bool common_semi_has_synccache(CPUArchState *env)
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{
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/* Ok for A64, invalid for A32/T32 */
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return is_a64(env);
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}
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