Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
89 lines
3.3 KiB
C
89 lines
3.3 KiB
C
/*
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* QEMU ARM OMAP CP15 register definitions
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "target/arm/cpu.h"
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#include "target/arm/cpregs.h"
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#include "target/arm/internals.h"
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static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c15_ticonfig = value & 0xe7;
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/* The OS_TYPE bit in this register changes the reported CPUID! */
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env->cp15.c0_cpuid = (value & (1 << 5)) ?
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ARM_CPUID_TI915T : ARM_CPUID_TI925T;
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}
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static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c15_threadid = value & 0xffff;
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}
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static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* Wait-for-interrupt (deprecated) */
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cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
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}
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static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* On OMAP there are registers indicating the max/min index of dcache lines
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* containing a dirty line; cache flush operations have to reset these.
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*/
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env->cp15.c15_i_max = 0x000;
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env->cp15.c15_i_min = 0xff0;
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}
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static const ARMCPRegInfo omap_cp_reginfo[] = {
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{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
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.resetvalue = 0, },
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{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_NOP },
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{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
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.writefn = omap_ticonfig_write },
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{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
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{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0xff0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
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{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
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.writefn = omap_threadid_write },
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{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
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.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
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.type = ARM_CP_NO_RAW,
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.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
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/*
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* TODO: Peripheral port remap register:
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* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
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* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
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* when MMU is off.
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*/
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{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
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.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
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.type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
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.writefn = omap_cachemaint_write },
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{ .name = "C9", .cp = 15, .crn = 9,
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.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
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.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
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};
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void define_omap_cp_regs(ARMCPU *cpu)
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{
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define_arm_cp_regs(cpu, omap_cp_reginfo);
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}
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