Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
134 lines
4.0 KiB
C
134 lines
4.0 KiB
C
/*
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* QEMU ARM 'max' CPU
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*
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* Copyright (c) 2018 Linaro Ltd
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/target-info.h"
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#include "system/hw_accel.h"
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#include "system/kvm.h"
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#include "system/qtest.h"
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#include "system/tcg.h"
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#include "target/arm/internals.h"
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#include "target/arm/cpregs.h"
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void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enabled)
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{
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ARMISARegisters *isar = &cpu->isar;
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
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if (aarch64_enabled) {
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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}
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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if (kvm_enabled()) {
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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}
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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SET_IDREG(isar, ID_PFR0, 0x00000131);
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SET_IDREG(isar, ID_PFR1, 0x00011011);
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SET_IDREG(isar, ID_DFR0, 0x03010066);
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SET_IDREG(isar, ID_AFR0, 0x00000000);
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SET_IDREG(isar, ID_MMFR0, 0x10101105);
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SET_IDREG(isar, ID_MMFR1, 0x40000000);
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SET_IDREG(isar, ID_MMFR2, 0x01260000);
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SET_IDREG(isar, ID_MMFR3, 0x02102211);
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SET_IDREG(isar, ID_ISAR0, 0x02101110);
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SET_IDREG(isar, ID_ISAR1, 0x13112111);
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SET_IDREG(isar, ID_ISAR2, 0x21232042);
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SET_IDREG(isar, ID_ISAR3, 0x01112131);
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SET_IDREG(isar, ID_ISAR4, 0x00011142);
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SET_IDREG(isar, ID_ISAR5, 0x00011121);
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SET_IDREG(isar, ID_ISAR6, 0);
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if (aarch64_enabled) {
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SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
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SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
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SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
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SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
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}
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x01110f13;
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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SET_IDREG(isar, CLIDR, 0x0a200023);
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 48KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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/* 2048KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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if (aarch64_enabled) {
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set_dczid_bs(cpu, 4); /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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}
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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/*
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* -cpu max: a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
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* this only needs to handle 32 bits, and need not care about KVM.
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*/
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static void cpu_max_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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const bool aarch64_enabled = target_aarch64();
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if (hwaccel_enabled()) {
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assert(aarch64_enabled);
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/*
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* When hardware acceleration enabled, '-cpu max' is
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* identical to '-cpu host'
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*/
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aarch64_host_initfn(obj);
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return;
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}
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if (tcg_enabled()) {
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if (!aarch64_enabled) {
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aarch32_max_tcg_init(cpu);
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} else {
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aarch64_max_tcg_initfn(obj);
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}
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return;
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}
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/* Ultimate fallback: -cpu max as cortex-a57. */
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assert(qtest_enabled());
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aarch64_aa32_a57_init(cpu, aarch64_enabled);
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}
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static const ARMCPUInfo arm_max_cpu = {
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.name = "max",
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.initfn = cpu_max_initfn,
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};
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static void arm_max_cpu_register_types(void)
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{
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arm_cpu_register(&arm_max_cpu);
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}
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type_init(arm_max_cpu_register_types)
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