Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
29 lines
642 B
C
29 lines
642 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define LoongArch target-specific operand constraints.
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*
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* Copyright (c) 2021 WANG Xuerui <[email protected]>
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*
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* Based on tcg/riscv/tcg-target-con-str.h
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*
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('w', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S12)
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CONST('J', TCG_CT_CONST_S32)
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CONST('U', TCG_CT_CONST_U12)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('M', TCG_CT_CONST_VCMP)
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CONST('A', TCG_CT_CONST_VADD)
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