Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
27 lines
658 B
C
27 lines
658 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define PowerPC target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */
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REGS('v', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('C', TCG_CT_CONST_CMP)
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CONST('I', TCG_CT_CONST_S16)
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CONST('M', TCG_CT_CONST_MONE)
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CONST('N', TCG_CT_CONST_N16)
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CONST('T', TCG_CT_CONST_S32)
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CONST('U', TCG_CT_CONST_U32)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('Z', TCG_CT_CONST_ZERO)
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