Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
22 lines
478 B
C
22 lines
478 B
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Define RISC-V target-specific operand constraints.
|
|
* Copyright (c) 2021 Linaro
|
|
*/
|
|
|
|
/*
|
|
* Define constraint letters for register sets:
|
|
* REGS(letter, register_mask)
|
|
*/
|
|
REGS('r', ALL_GENERAL_REGS)
|
|
REGS('v', ALL_VECTOR_REGS)
|
|
|
|
/*
|
|
* Define constraint letters for constants:
|
|
* CONST(letter, TCG_CT_CONST_* bit set)
|
|
*/
|
|
CONST('I', TCG_CT_CONST_S12)
|
|
CONST('K', TCG_CT_CONST_S5)
|
|
CONST('L', TCG_CT_CONST_CMP_VI)
|
|
CONST('M', TCG_CT_CONST_M12)
|