Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
20 lines
498 B
C
20 lines
498 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific memory model
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef TCG_TARGET_MO_H
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#define TCG_TARGET_MO_H
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/*
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* This defines the natural memory order supported by this architecture
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* before guarantees made by various barrier instructions.
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*
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* The x86 has a pretty strong memory ordering which only really
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* allows for some stores to be re-ordered after loads.
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*/
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#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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#endif
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