Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
58 lines
1.7 KiB
Python
58 lines
1.7 KiB
Python
#!/usr/bin/env python3
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#
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# Functional tests for RISC-V big-endian support
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#
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# Copyright (c) 2026 MIPS
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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from qemu_test import QemuSystemTest, Asset
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from qemu_test import wait_for_console_pattern
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class RiscvBigEndian(QemuSystemTest):
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"""
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Tests for RISC-V runtime big-endian data support.
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Uses a bare-metal RV64 ELF that detects data endianness at runtime
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by storing a 32-bit word and reading back byte 0. Prints "ENDIAN: BE"
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or "ENDIAN: LE" to the NS16550A UART on the virt machine.
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"""
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timeout = 10
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ASSET_BE_TEST = Asset(
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'https://github.com/MIPS/linux-test-downloads/raw/main/'
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'riscvbe-baremetal/be-test-bare-metal.elf',
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'9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58')
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def _run_bare_metal(self, big_endian=False):
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self.set_machine('virt')
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kernel = self.ASSET_BE_TEST.fetch()
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self.vm.add_args('-bios', 'none')
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self.vm.add_args('-kernel', kernel)
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if big_endian:
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self.vm.add_args('-cpu', 'rv64,big-endian=on')
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self.vm.set_console()
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self.vm.launch()
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expected = 'ENDIAN: BE' if big_endian else 'ENDIAN: LE'
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wait_for_console_pattern(self, expected)
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def test_bare_metal_littleendian(self):
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"""
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Boot bare-metal ELF on virt with default little-endian CPU.
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Expects "ENDIAN: LE" on UART.
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"""
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self._run_bare_metal(big_endian=False)
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def test_bare_metal_bigendian(self):
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"""
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Boot bare-metal ELF on virt with big-endian=on CPU property.
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Expects "ENDIAN: BE" on UART.
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"""
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self._run_bare_metal(big_endian=True)
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if __name__ == '__main__':
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QemuSystemTest.main()
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