Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
104 lines
3.6 KiB
C
104 lines
3.6 KiB
C
/*
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* QTest testcase for the ASPEED Hash and Crypto Engine
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Copyright 2021 IBM Corp.
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*/
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#ifndef TESTS_ASPEED_HACE_UTILS_H
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#define TESTS_ASPEED_HACE_UTILS_H
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#include "libqtest.h"
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#include "qemu/bitops.h"
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#define HACE_CMD 0x10
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#define HACE_SHA_BE_EN BIT(3)
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#define HACE_MD5_LE_EN BIT(2)
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#define HACE_ALGO_MD5 0
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#define HACE_ALGO_SHA1 BIT(5)
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#define HACE_ALGO_SHA224 BIT(6)
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#define HACE_ALGO_SHA256 (BIT(4) | BIT(6))
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#define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
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#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
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#define HACE_SG_EN BIT(18)
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#define HACE_ACCUM_EN BIT(8)
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#define HACE_STS 0x1c
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#define HACE_RSA_ISR BIT(13)
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#define HACE_CRYPTO_ISR BIT(12)
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#define HACE_HASH_ISR BIT(9)
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#define HACE_RSA_BUSY BIT(2)
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#define HACE_CRYPTO_BUSY BIT(1)
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#define HACE_HASH_BUSY BIT(0)
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#define HACE_HASH_SRC 0x20
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#define HACE_HASH_DIGEST 0x24
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#define HACE_HASH_KEY_BUFF 0x28
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#define HACE_HASH_DATA_LEN 0x2c
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#define HACE_HASH_CMD 0x30
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#define HACE_HASH_SRC_HI 0x90
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#define HACE_HASH_DIGEST_HI 0x94
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#define HACE_HASH_KEY_BUFF_HI 0x98
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/* Scatter-Gather Hash */
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#define SG_LIST_LEN_LAST BIT(31)
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struct AspeedSgList {
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uint32_t len;
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uint32_t addr;
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} __attribute__ ((__packed__));
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struct AspeedMasks {
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uint32_t src;
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uint32_t dest;
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uint32_t key;
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uint32_t len;
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uint32_t src_hi;
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uint32_t dest_hi;
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uint32_t key_hi;
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};
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void aspeed_test_md5(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha256(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha384(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha512(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
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const uint64_t src_addr);
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void aspeed_test_addresses(const char *machine, const uint32_t base,
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const struct AspeedMasks *expected);
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/*
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* Cipher modes a SoC's crypto engine supports, for aspeed_add_crypto_tests().
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*/
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enum {
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CRYPT_MODE_ECB = 1 << 0,
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CRYPT_MODE_CBC = 1 << 1,
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CRYPT_MODE_CTR = 1 << 2,
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CRYPT_MODE_GCM = 1 << 3,
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};
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/*
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* Register the crypto known-answer tests that @modes selects (a mask of
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* CRYPT_MODE_*) for the given machine. Each test is named
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* "<prefix>/hace/crypto/<mode>". @sg selects scatter-gather mode (used by the
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* AST2600 and later) instead of the AST2500 direct access mode.
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*/
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void aspeed_add_crypto_tests(const char *prefix, const char *machine,
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uint32_t base, uint64_t dram, uint32_t modes,
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bool sg);
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#endif /* TESTS_ASPEED_HACE_UTILS_H */
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