Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* QTest for SMMUv3 with iommu-testdev
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*
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* This QTest file is used to test the SMMUv3 with iommu-testdev so that we can
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* test SMMUv3 without any guest kernel or firmware.
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*
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* Copyright (c) 2026 Phytium Technology
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*
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* Author:
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* Tao Tang <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci.h"
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#include "libqos/generic-pcihost.h"
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#include "hw/pci/pci_regs.h"
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#include "hw/misc/iommu-testdev.h"
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#include "libqos/qos-smmuv3.h"
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#define DMA_LEN 4
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static uint64_t smmuv3_expected_gpa(uint64_t iova)
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{
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return qsmmu_space_offset(QSMMU_SPACE_NONSECURE) +
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QSMMU_L3_PTE_VAL + (iova & 0xfff);
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}
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static void save_fn(QPCIDevice *dev, int devfn, void *data)
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{
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QPCIDevice **pdev = (QPCIDevice **) data;
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*pdev = dev;
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}
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static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QGenericPCIBus *gbus,
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QPCIBar *bar)
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{
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QPCIDevice *dev = NULL;
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qpci_init_generic(gbus, qts, NULL, false);
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qpci_device_foreach(&gbus->bus, IOMMU_TESTDEV_VENDOR_ID,
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IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);
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g_assert(dev);
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qpci_device_enable(dev);
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*bar = qpci_iomap(dev, 0, NULL);
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g_assert_false(bar->is_io);
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return dev;
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}
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static void run_smmuv3_translation(const QSMMUTestConfig *cfg)
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{
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QTestState *qts;
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QGenericPCIBus gbus;
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QPCIDevice *dev;
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QPCIBar bar;
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if (!qtest_has_machine("virt")) {
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g_test_skip("virt machine not available");
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return;
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}
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if (!qtest_has_device("arm-gicv3")) {
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/* This can happen for a KVM-only build: qtest uses the TCG GICv3 */
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g_test_skip("gicv3 not available");
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return;
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}
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/* Initialize QEMU environment for SMMU testing */
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qts = qtest_init("-machine virt,acpi=off,gic-version=3,iommu=smmuv3 "
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"-smp 1 -m 512 -cpu max -net none "
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"-device iommu-testdev");
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/* Setup and configure PCI device */
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dev = setup_qtest_pci_device(qts, &gbus, &bar);
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g_assert(dev);
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g_test_message("### SMMUv3 translation mode=%d sec_sid=%d ###",
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cfg->trans_mode, cfg->sec_sid);
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qsmmu_run_translation_case(qts, dev, bar, VIRT_SMMU_BASE, cfg);
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g_free(dev);
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qtest_quit(qts);
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}
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static void test_smmuv3_ns_s1_only(void)
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{
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QSMMUTestConfig cfg = {
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.trans_mode = QSMMU_TM_S1_ONLY,
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.sec_sid = QSMMU_SEC_SID_NONSECURE,
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.dma_gpa = smmuv3_expected_gpa(QSMMU_IOVA),
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.dma_len = DMA_LEN,
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.expected_result = 0,
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};
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run_smmuv3_translation(&cfg);
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}
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static void test_smmuv3_ns_s2_only(void)
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{
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QSMMUTestConfig cfg = {
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.trans_mode = QSMMU_TM_S2_ONLY,
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.sec_sid = QSMMU_SEC_SID_NONSECURE,
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.dma_gpa = smmuv3_expected_gpa(QSMMU_IOVA),
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.dma_len = DMA_LEN,
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.expected_result = 0,
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};
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run_smmuv3_translation(&cfg);
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}
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static void test_smmuv3_ns_nested(void)
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{
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QSMMUTestConfig cfg = {
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.trans_mode = QSMMU_TM_NESTED,
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.sec_sid = QSMMU_SEC_SID_NONSECURE,
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.dma_gpa = smmuv3_expected_gpa(QSMMU_IOVA),
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.dma_len = DMA_LEN,
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.expected_result = 0,
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};
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run_smmuv3_translation(&cfg);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/iommu-testdev/translation/ns-s1-only",
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test_smmuv3_ns_s1_only);
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qtest_add_func("/iommu-testdev/translation/ns-s2-only",
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test_smmuv3_ns_s2_only);
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qtest_add_func("/iommu-testdev/translation/ns-nested",
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test_smmuv3_ns_nested);
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return g_test_run();
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}
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