Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
190 lines
6.1 KiB
C
190 lines
6.1 KiB
C
/*
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* QTest testcase for K230 Watchdog
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*
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* Copyright (c) 2025 Mig Yang <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Provides a board compatible with the kendryte K230 SDK
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*
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* K230 Technical Reference Manual V0.3.1 (2024-11-18):
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* https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
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*
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* For more information, see <https://www.kendryte.com/en/proDetail/230>
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "libqtest.h"
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#include "hw/watchdog/k230_wdt.h"
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/* K230 WDT0 base address */
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#define K230_WDT0_BASE 0x91106000
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#define K230_WDT1_BASE 0x91106800
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/* Test WDT0 by default */
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#define WDT_BASE K230_WDT0_BASE
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static void test_register_read_write(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Test Control Register (CR) read/write */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, 0xFFFFFFFF);
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g_assert_cmphex(qtest_readl(qts, WDT_BASE + K230_WDT_CR), ==,
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(K230_WDT_CR_RPL_MASK << K230_WDT_CR_RPL_SHIFT) |
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K230_WDT_CR_RMOD | K230_WDT_CR_WDT_EN);
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/* Test Timeout Range Register (TORR) read/write */
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qtest_writel(qts, WDT_BASE + K230_WDT_TORR, 0xFFFFFFFF);
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g_assert_cmphex(qtest_readl(qts, WDT_BASE + K230_WDT_TORR), ==,
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K230_WDT_TORR_TOP_MASK);
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/* Test Protection Level Register read/write */
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qtest_writel(qts, WDT_BASE + K230_WDT_PROT_LEVEL, 0xFFFFFFFF);
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g_assert_cmphex(qtest_readl(qts, WDT_BASE + K230_WDT_PROT_LEVEL), ==, 0x7);
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qtest_quit(qts);
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}
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static void test_counter_restart(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Enable watchdog and set timeout */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, K230_WDT_CR_WDT_EN);
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qtest_writel(qts, WDT_BASE + K230_WDT_TORR, 0x5); /* TOP = 5 */
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/* Read current counter value */
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uint32_t initial_count = qtest_readl(qts, WDT_BASE + K230_WDT_CCVR);
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g_assert_cmpuint(initial_count, >, 0);
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/* Restart counter with magic value */
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qtest_writel(qts, WDT_BASE + K230_WDT_CRR, K230_WDT_CRR_RESTART);
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/* Wait for time */
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qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 2);
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/* Counter should be reset to timeout value */
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uint32_t new_count = qtest_readl(qts, WDT_BASE + K230_WDT_CCVR);
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g_assert_cmpuint(new_count, >, 0);
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g_assert_cmpuint(new_count, !=, initial_count);
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qtest_quit(qts);
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}
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static void test_interrupt_mode(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Set interrupt mode and enable watchdog */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR,
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K230_WDT_CR_RMOD | K230_WDT_CR_WDT_EN);
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qtest_writel(qts, WDT_BASE + K230_WDT_TORR, 0x1); /* Short timeout */
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/* Wait for timeout to trigger interrupt */
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qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 10);
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/* Check interrupt status */
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uint32_t stat = qtest_readl(qts, WDT_BASE + K230_WDT_STAT);
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g_assert_cmphex(stat & K230_WDT_STAT_INT, ==, K230_WDT_STAT_INT);
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/* Clear interrupt */
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qtest_writel(qts, WDT_BASE + K230_WDT_EOI, 0x1);
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stat = qtest_readl(qts, WDT_BASE + K230_WDT_STAT);
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g_assert_cmphex(stat & K230_WDT_STAT_INT, ==, 0);
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qtest_quit(qts);
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}
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static void test_reset_mode(void)
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{
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QTestState *qts = qtest_init("-machine k230 -no-reboot");
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/* Set reset mode and enable watchdog */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, K230_WDT_CR_WDT_EN);
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qtest_writel(qts, WDT_BASE + K230_WDT_TORR, 0x1); /* Short timeout */
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/* Wait for timeout to trigger reset */
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qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 2);
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/* In reset mode, the system should reset */
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/* This test verifies that reset mode is properly configured */
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qtest_quit(qts);
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}
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static void test_timeout_calculation(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Test different timeout values */
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for (uint32_t top = 0; top <= 15; top++) {
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qtest_writel(qts, WDT_BASE + K230_WDT_TORR, top);
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, K230_WDT_CR_WDT_EN);
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/* Read current counter value */
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uint32_t count = qtest_readl(qts, WDT_BASE + K230_WDT_CCVR);
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g_assert_cmpuint(count, >, 0);
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/* Disable watchdog for next iteration */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, 0);
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}
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qtest_quit(qts);
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}
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static void test_wdt1_registers(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Test WDT1 registers (second watchdog) */
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qtest_writel(qts, K230_WDT1_BASE + K230_WDT_CR, 0xFFFFFFFF);
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g_assert_cmphex(qtest_readl(qts, K230_WDT1_BASE + K230_WDT_CR), ==,
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(K230_WDT_CR_RPL_MASK << K230_WDT_CR_RPL_SHIFT) |
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K230_WDT_CR_RMOD | K230_WDT_CR_WDT_EN);
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qtest_writel(qts, K230_WDT1_BASE + K230_WDT_TORR, 0xFFFFFFFF);
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g_assert_cmphex(qtest_readl(qts, K230_WDT1_BASE + K230_WDT_TORR), ==,
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K230_WDT_TORR_TOP_MASK);
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qtest_quit(qts);
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}
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static void test_enable_disable(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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/* Initially disabled */
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uint32_t cr = qtest_readl(qts, WDT_BASE + K230_WDT_CR);
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g_assert_cmphex(cr & K230_WDT_CR_WDT_EN, ==, 0);
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/* Enable watchdog */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, K230_WDT_CR_WDT_EN);
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cr = qtest_readl(qts, WDT_BASE + K230_WDT_CR);
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g_assert_cmphex(cr & K230_WDT_CR_WDT_EN, ==, K230_WDT_CR_WDT_EN);
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/* Disable watchdog */
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qtest_writel(qts, WDT_BASE + K230_WDT_CR, 0);
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cr = qtest_readl(qts, WDT_BASE + K230_WDT_CR);
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g_assert_cmphex(cr & K230_WDT_CR_WDT_EN, ==, 0);
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qtest_quit(qts);
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}
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int main(int argc, char *argv[])
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/k230-wdt/register_read_write", test_register_read_write);
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qtest_add_func("/k230-wdt/counter_restart", test_counter_restart);
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qtest_add_func("/k230-wdt/interrupt_mode", test_interrupt_mode);
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qtest_add_func("/k230-wdt/reset_mode", test_reset_mode);
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qtest_add_func("/k230-wdt/timeout_calculation", test_timeout_calculation);
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qtest_add_func("/k230-wdt/wdt1_registers", test_wdt1_registers);
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qtest_add_func("/k230-wdt/enable_disable", test_enable_disable);
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return g_test_run();
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}
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