Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/*
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* Aspeed i2c bus interface to reading and writing to i2c device registers
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*
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* Copyright (c) 2023 IBM Corporation
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*
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* Authors:
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* Stefan Berger <[email protected]>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef QTEST_ASPEED_H
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#define QTEST_ASPEED_H
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#include "libqtest.h"
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#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
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/* Implements only AST2600 I2C controller */
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static inline uint32_t ast2600_i2c_calc_bus_addr(uint8_t bus_num)
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{
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return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
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}
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uint8_t aspeed_i2c_readb(QTestState *s,
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uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
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uint16_t aspeed_i2c_readw(QTestState *s,
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uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
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uint32_t aspeed_i2c_readl(QTestState *s,
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uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
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void aspeed_i2c_writeb(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
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uint8_t reg, uint8_t v);
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void aspeed_i2c_writew(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
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uint8_t reg, uint16_t v);
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void aspeed_i2c_writel(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
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uint8_t reg, uint32_t v);
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#endif
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