Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
95 lines
5.7 KiB
ReStructuredText
95 lines
5.7 KiB
ReStructuredText
===========================
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ASPEED Interrupt Controller
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===========================
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AST2700
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-------
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There are a total of 480 interrupt sources in AST2700. Due to the limitation of
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interrupt numbers of processors, the interrupts are merged every 32 sources for
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interrupt numbers greater than 127.
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There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO
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(I/O Die).
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Interrupt Mapping
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-----------------
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- INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO.
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- INTCIO: Handles interrupt sources 128 - 319 independently.
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QEMU Support
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------------
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Currently, only GIC 192 to 201 are supported, and their source interrupts are
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from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
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GIC 192-201.
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Design for GICINT 196
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---------------------
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The orgate has interrupt sources ranging from 0 to 31, with its output pin
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connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC
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"GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196.
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INTC GIC_192_201 Output Pin Mapping
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-----------------------------------
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The design of INTC GIC_192_201 have 10 output pins, mapped as following:
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==== ====
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Bit GIC
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==== ====
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0 192
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1 193
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2 194
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3 195
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4 196
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5 197
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6 198
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7 199
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8 200
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9 201
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==== ====
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Block Diagram of GICINT 196 for AST2700 A1
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------------------------------------------------------------------------
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.. code-block::
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|-------------------------------------------------------------------------------------------------------|
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| AST2700 A1 Design |
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| To GICINT196 |
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| ETH1 |-----------| |--------------------------| |--------------| |
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| ------->|0 | | INTCIO | | orgates[0] | |
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| ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
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| ------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
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| ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
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| ------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
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| UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
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| ------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
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| UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
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| ------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
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| UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
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| ------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
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| UART3 | 26| |--------------------------| |--------------| | |
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| ------->|10 27| | |
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| UART5 | 28| | |
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| ------->|11 29| | |
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| UART6 | | | |
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| ------->|12 30| |-----------------------------------------------------------------------| |
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| UART7 | 31| | |
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| ------->|13 | | |
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| UART8 | OR[0:31] | | |-----------------------------| |----------| |
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| ------->|14 | | | INTC | | GIC | |
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| UART9 | | | |inpin[0:0]--------->outpin[0]|--------->|192 | |
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| ------->|15 | | |inpin[0:1]--------->outpin[1]|--------->|193 | |
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| UART10 | | | |inpin[0:2]--------->outpin[2]|--------->|194 | |
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| ------->|16 | | |inpin[0:3]--------->outpin[3]|--------->|195 | |
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| UART11 | | |--------------> |inpin[0:4]--------->outpin[4]|--------->|196 | |
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| ------->|17 | |inpin[0:5]--------->outpin[5]|--------->|197 | |
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| UART12 | | |inpin[0:6]--------->outpin[6]|--------->|198 | |
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| ------->|18 | |inpin[0:7]--------->outpin[7]|--------->|199 | |
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| |-----------| |inpin[0:8]--------->outpin[8]|--------->|200 | |
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| |inpin[0:9]--------->outpin[9]|--------->|201 | |
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| |-----------------------------| |----------| |
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|-------------------------------------------------------------------------------------------------------|
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