Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
244 lines
7.9 KiB
C
244 lines
7.9 KiB
C
/*
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* Axiado SoC AX3000
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*
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* Author: Kuan-Jui Chiu <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "system/address-spaces.h"
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#include "hw/arm/bsa.h"
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#include "hw/arm/ax3000-soc.h"
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#include "hw/misc/unimp.h"
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#include "system/system.h"
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#include "qobject/qlist.h"
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#include "qom/object.h"
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#include "hw/core/boards.h"
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static void ax3000_init(Object *obj)
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{
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Ax3000SoCState *s = AX3000_SOC(obj);
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Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
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for (int i = 0; i < sc->num_cpus; i++) {
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g_autofree char *name = g_strdup_printf("cpu%d", i);
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object_initialize_child(obj, name, &s->cpu[i],
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ARM_CPU_TYPE_NAME("cortex-a53"));
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}
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object_initialize_child(obj, "gic", &s->gic, gicv3_class_name());
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for (int i = 0; i < AX3000_NUM_UARTS; i++) {
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g_autofree char *name = g_strdup_printf("uart%d", i);
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object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART);
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}
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object_initialize_child(obj, "clk", &s->ax3000_clk, TYPE_AX3000_CLK);
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object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI);
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for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
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g_autofree char *name = g_strdup_printf("gpio%d", i);
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object_initialize_child(obj, name, &s->gpio[i], TYPE_CADENCE_GPIO);
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}
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}
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static void ax3000_realize(DeviceState *dev, Error **errp)
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{
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Ax3000SoCState *s = AX3000_SOC(dev);
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Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
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SysBusDevice *gic_sbd = SYS_BUS_DEVICE(&s->gic);
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DeviceState *gic_dev = DEVICE(&s->gic);
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QList *redist_region_count;
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SysBusDevice *sdhci0_sbd;
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DeviceState *card;
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DriveInfo *dinfo;
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/* CPUs */
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for (int i = 0; i < sc->num_cpus; i++) {
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object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000,
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&error_abort);
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if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) {
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object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3",
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false, &error_abort);
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}
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if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
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return;
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}
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}
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/* GIC */
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qdev_prop_set_uint32(gic_dev, "num-cpu", sc->num_cpus);
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qdev_prop_set_uint32(gic_dev, "num-irq",
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AX3000_NUM_IRQS + GIC_INTERNAL);
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redist_region_count = qlist_new();
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qlist_append_int(redist_region_count, sc->num_cpus);
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qdev_prop_set_array(gic_dev, "redist-region-count", redist_region_count);
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if (!sysbus_realize(gic_sbd, errp)) {
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return;
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}
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sysbus_mmio_map(gic_sbd, 0, AX3000_GIC_DIST_BASE);
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sysbus_mmio_map(gic_sbd, 1, AX3000_GIC_REDIST_BASE);
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/*
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* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs.
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*/
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const int timer_irqs[] = {
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[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
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[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
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[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
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[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ
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};
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/*
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* Wire the outputs from each CPU's generic timer and the GICv3
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* maintenance interrupt signal to the appropriate GIC PPI inputs, and
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* the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.
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*/
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for (int i = 0; i < sc->num_cpus; i++) {
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DeviceState *cpu_dev = DEVICE(&s->cpu[i]);
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int intidbase = AX3000_NUM_IRQS + i * GIC_INTERNAL;
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qemu_irq irq;
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for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {
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irq = qdev_get_gpio_in(gic_dev, intidbase + timer_irqs[j]);
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qdev_connect_gpio_out(cpu_dev, j, irq);
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}
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irq = qdev_get_gpio_in(gic_dev, intidbase + ARCH_GIC_MAINT_IRQ);
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qdev_connect_gpio_out_named(cpu_dev, "gicv3-maintenance-interrupt",
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0, irq);
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sysbus_connect_irq(gic_sbd, i,
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qdev_get_gpio_in(cpu_dev, ARM_CPU_IRQ));
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sysbus_connect_irq(gic_sbd, i + sc->num_cpus,
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qdev_get_gpio_in(cpu_dev, ARM_CPU_FIQ));
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sysbus_connect_irq(gic_sbd, i + 2 * sc->num_cpus,
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qdev_get_gpio_in(cpu_dev, ARM_CPU_VIRQ));
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sysbus_connect_irq(gic_sbd, i + 3 * sc->num_cpus,
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qdev_get_gpio_in(cpu_dev, ARM_CPU_VFIQ));
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}
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/* DRAM */
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const struct {
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hwaddr addr;
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size_t size;
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const char *name;
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} dram_table[] = {
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{ AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, "dram0" },
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{ AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, "dram1" }
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};
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for (int i = 0; i < AX3000_NUM_BANKS; i++) {
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memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name,
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dram_table[i].size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), dram_table[i].addr,
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&s->dram[i]);
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}
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/* UARTs */
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const struct {
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hwaddr addr;
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unsigned int irq;
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} serial_table[] = {
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{ AX3000_UART0_BASE, AX3000_UART0_IRQ },
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{ AX3000_UART1_BASE, AX3000_UART1_IRQ },
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{ AX3000_UART2_BASE, AX3000_UART2_IRQ },
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{ AX3000_UART3_BASE, AX3000_UART3_IRQ }
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};
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for (int i = 0; i < AX3000_NUM_UARTS; i++) {
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
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qdev_get_gpio_in(gic_dev, serial_table[i].irq));
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}
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/* Timer control */
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create_unimplemented_device("ax3000.timerctrl", AX3000_TIMER_CTRL, 32);
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/* Clock control */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->ax3000_clk), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ax3000_clk), 0, AX3000_PLL_BASE);
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/* SDHCI */
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sdhci0_sbd = SYS_BUS_DEVICE(&s->sdhci0);
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if (!sysbus_realize(sdhci0_sbd, errp)) {
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return;
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}
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sysbus_mmio_map(sdhci0_sbd, 0, AX3000_SDHCI0_BASE);
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sysbus_mmio_map(sdhci0_sbd, 1, AX3000_EMMC_PHY_BASE);
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sysbus_connect_irq(sdhci0_sbd, 0,
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qdev_get_gpio_in(gic_dev, AX3000_SDHCI0_IRQ));
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dinfo = drive_get(IF_SD, 0, 0);
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if (dinfo) {
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card = qdev_new(TYPE_SD_CARD);
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qdev_prop_set_drive_err(card, "drive",
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blk_by_legacy_dinfo(dinfo),
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&error_fatal);
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qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);
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}
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/* GPIOs */
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const struct {
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hwaddr addr;
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unsigned int irq;
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} gpio_table[] = {
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{ AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ },
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{ AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ },
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{ AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ },
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{ AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ },
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{ AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ },
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{ AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ },
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{ AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ },
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{ AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ }
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};
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for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
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qdev_get_gpio_in(gic_dev, gpio_table[i].irq));
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}
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}
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static void ax3000_class_init(ObjectClass *oc, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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Ax3000SoCClass *sc = AX3000_SOC_CLASS(oc);
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dc->desc = "Axiado SoC AX3000";
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dc->realize = ax3000_realize;
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sc->num_cpus = AX3000_NUM_CPUS;
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}
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static const TypeInfo axiado_soc_types[] = {
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{
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.name = TYPE_AX3000_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Ax3000SoCState),
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.instance_init = ax3000_init,
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.class_init = ax3000_class_init,
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.class_size = sizeof(Ax3000SoCClass),
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}
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};
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DEFINE_TYPES(axiado_soc_types)
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