Yaya48
5d9a60a926
Model the A6 crypto, interrupt, USB, and platform blocks needed to boot SecureROM through iBSS into iBEC Recovery. Add local lab identity, IMG3, and APTicket tooling, patched macOS recovery utilities, UART and GDB access, and English end-user documentation.
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* Apple S5L8950X I2C controller (minimal polled-transfer model)
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*
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* Early iBoot uses the three controllers while bringing up board devices.
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* The target devices are not modelled yet, so reads return zero, but command
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* FIFO writes complete synchronously and without a NAK. This is sufficient
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* to preserve the firmware's normal timeout/error paths while allowing the
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* boot chain to continue through board discovery.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/arm/s5l8950x.h"
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#include "hw/core/irq.h"
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#include "hw/core/sysbus.h"
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#include "qom/object.h"
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#define S5L8950X_I2C_REGION_SIZE 0x1000
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#define S5L8950X_I2C_STATUS 0x14
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#define S5L8950X_I2C_STATUS_DONE BIT(27)
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OBJECT_DECLARE_SIMPLE_TYPE(S5L8950XI2CState, S5L8950X_I2C)
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struct S5L8950XI2CState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t regs[S5L8950X_I2C_REGION_SIZE / sizeof(uint32_t)];
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};
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static uint64_t s5l8950x_i2c_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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S5L8950XI2CState *s = opaque;
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uint32_t value = s->regs[offset / sizeof(uint32_t)];
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if (offset == S5L8950X_I2C_STATUS) {
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value |= S5L8950X_I2C_STATUS_DONE;
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}
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return value;
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}
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static void s5l8950x_i2c_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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S5L8950XI2CState *s = opaque;
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if (offset == S5L8950X_I2C_STATUS) {
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s->regs[offset / sizeof(uint32_t)] &= ~value;
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if (!(s->regs[offset / sizeof(uint32_t)] &
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S5L8950X_I2C_STATUS_DONE)) {
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qemu_irq_lower(s->irq);
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}
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return;
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}
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s->regs[offset / sizeof(uint32_t)] = value;
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if (offset == 0) {
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s->regs[S5L8950X_I2C_STATUS / sizeof(uint32_t)] |=
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S5L8950X_I2C_STATUS_DONE;
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qemu_irq_raise(s->irq);
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}
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}
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static const MemoryRegionOps s5l8950x_i2c_ops = {
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.read = s5l8950x_i2c_read,
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.write = s5l8950x_i2c_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void s5l8950x_i2c_reset(DeviceState *dev)
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{
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S5L8950XI2CState *s = S5L8950X_I2C(dev);
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memset(s->regs, 0, sizeof(s->regs));
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qemu_irq_lower(s->irq);
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}
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static void s5l8950x_i2c_init(Object *obj)
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{
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S5L8950XI2CState *s = S5L8950X_I2C(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &s5l8950x_i2c_ops, s,
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TYPE_S5L8950X_I2C, S5L8950X_I2C_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void s5l8950x_i2c_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, s5l8950x_i2c_reset);
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}
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static const TypeInfo s5l8950x_i2c_info = {
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.name = TYPE_S5L8950X_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(S5L8950XI2CState),
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.instance_init = s5l8950x_i2c_init,
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.class_init = s5l8950x_i2c_class_init,
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};
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static void s5l8950x_i2c_register_types(void)
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{
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type_register_static(&s5l8950x_i2c_info);
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}
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type_init(s5l8950x_i2c_register_types)
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