Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
59 lines
1.1 KiB
C
59 lines
1.1 KiB
C
/*
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* Renesas 8bit timer Object
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*
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* Copyright (c) 2018 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_TIMER_RENESAS_TMR_H
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#define HW_TIMER_RENESAS_TMR_H
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#include "qemu/timer.h"
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#include "hw/core/sysbus.h"
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#include "qom/object.h"
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#define TYPE_RENESAS_TMR "renesas-tmr"
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typedef struct RTMRState RTMRState;
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DECLARE_INSTANCE_CHECKER(RTMRState, RTMR,
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TYPE_RENESAS_TMR)
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enum timer_event {
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cmia = 0,
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cmib = 1,
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ovi = 2,
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none = 3,
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TMR_NR_EVENTS = 4
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};
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enum {
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TMR_CH = 2,
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TMR_NR_IRQ = 3 * TMR_CH
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};
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struct RTMRState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint64_t input_freq;
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MemoryRegion memory;
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int64_t tick;
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uint8_t tcnt[TMR_CH];
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uint8_t tcora[TMR_CH];
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uint8_t tcorb[TMR_CH];
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uint8_t tcr[TMR_CH];
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uint8_t tccr[TMR_CH];
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uint8_t tcor[TMR_CH];
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uint8_t tcsr[TMR_CH];
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int64_t div_round[TMR_CH];
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uint8_t next[TMR_CH];
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qemu_irq cmia[TMR_CH];
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qemu_irq cmib[TMR_CH];
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qemu_irq ovi[TMR_CH];
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QEMUTimer timer[TMR_CH];
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};
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#endif
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