Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* ARM MemTag convenience functions.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef AARCH64_MTE_USER_HELPER_H
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#define AARCH64_MTE USER_HELPER_H
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#include "user/abitypes.h"
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#ifndef PR_MTE_TCF_SHIFT
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# define PR_MTE_TCF_SHIFT 1
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# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TAG_SHIFT 3
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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#endif
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#ifndef PR_MTE_STORE_ONLY
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# define PR_MTE_STORE_ONLY (1UL << 19)
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#endif
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/**
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* arm_set_tagged_addr_ctrl - Set TCF0 and TCSO0 fields in SCTLR_EL1 register
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* @env: The CPU environment
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* @value: The value to be set for the Tag Check Fault and Tag Check Store Only
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* in EL0 field.
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*
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* Only SYNC and ASYNC modes can be selected for TCF0. If ASYMM mode is given,
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* the SYNC mode is selected instead. So, there is no way to set the ASYMM mode.
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*/
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void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value);
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#endif /* AARCH64_MTE_USER_HELPER_H */
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