Merge pull request #1307 from comex/bitset

Higher level bitset wrapper

Source/Core/Core/PowerPC/Jit64/Jit.cpp

@@ -241,9 +241,9 @@ void Jit64::WriteCallInterpreter(UGeckoInstruction inst)
 		MOV(32, PPCSTATE(npc), Imm32(js.compilerPC + 4));
 	}
 	Interpreter::_interpreterInstruction instr = GetInterpreterOp(inst);
-	ABI_PushRegistersAndAdjustStack(0, 0);
+	ABI_PushRegistersAndAdjustStack({}, 0);
 	ABI_CallFunctionC((void*)instr, inst.hex);
-	ABI_PopRegistersAndAdjustStack(0, 0);
+	ABI_PopRegistersAndAdjustStack({}, 0);
 }
 
 void Jit64::unknown_instruction(UGeckoInstruction inst)
@@ -260,9 +260,9 @@ void Jit64::HLEFunction(UGeckoInstruction _inst)
 {
 	gpr.Flush();
 	fpr.Flush();
-	ABI_PushRegistersAndAdjustStack(0, 0);
+	ABI_PushRegistersAndAdjustStack({}, 0);
 	ABI_CallFunctionCC((void*)&HLE::Execute, js.compilerPC, _inst.hex);
-	ABI_PopRegistersAndAdjustStack(0, 0);
+	ABI_PopRegistersAndAdjustStack({}, 0);
 }
 
 void Jit64::DoNothing(UGeckoInstruction _inst)
@@ -300,18 +300,18 @@ bool Jit64::Cleanup()
 
 	if (jo.optimizeGatherPipe && js.fifoBytesThisBlock > 0)
 	{
-		ABI_PushRegistersAndAdjustStack(0, 0);
+		ABI_PushRegistersAndAdjustStack({}, 0);
 		ABI_CallFunction((void *)&GPFifo::CheckGatherPipe);
-		ABI_PopRegistersAndAdjustStack(0, 0);
+		ABI_PopRegistersAndAdjustStack({}, 0);
 		did_something = true;
 	}
 
 	// SPEED HACK: MMCR0/MMCR1 should be checked at run-time, not at compile time.
 	if (MMCR0.Hex || MMCR1.Hex)
 	{
-		ABI_PushRegistersAndAdjustStack(0, 0);
+		ABI_PushRegistersAndAdjustStack({}, 0);
 		ABI_CallFunctionCCC((void *)&PowerPC::UpdatePerformanceMonitor, js.downcountAmount, jit->js.numLoadStoreInst, jit->js.numFloatingPointInst);
-		ABI_PopRegistersAndAdjustStack(0, 0);
+		ABI_PopRegistersAndAdjustStack({}, 0);
 		did_something = true;
 	}
 
@@ -426,9 +426,9 @@ void Jit64::WriteRfiExitDestInRSCRATCH()
 	MOV(32, PPCSTATE(pc), R(RSCRATCH));
 	MOV(32, PPCSTATE(npc), R(RSCRATCH));
 	Cleanup();
-	ABI_PushRegistersAndAdjustStack(0, 0);
+	ABI_PushRegistersAndAdjustStack({}, 0);
 	ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
-	ABI_PopRegistersAndAdjustStack(0, 0);
+	ABI_PopRegistersAndAdjustStack({}, 0);
 	SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount));
 	JMP(asm_routines.dispatcher, true);
 }
@@ -438,9 +438,9 @@ void Jit64::WriteExceptionExit()
 	Cleanup();
 	MOV(32, R(RSCRATCH), PPCSTATE(pc));
 	MOV(32, PPCSTATE(npc), R(RSCRATCH));
-	ABI_PushRegistersAndAdjustStack(0, 0);
+	ABI_PushRegistersAndAdjustStack({}, 0);
 	ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
-	ABI_PopRegistersAndAdjustStack(0, 0);
+	ABI_PopRegistersAndAdjustStack({}, 0);
 	SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount));
 	JMP(asm_routines.dispatcher, true);
 }
@@ -450,9 +450,9 @@ void Jit64::WriteExternalExceptionExit()
 	Cleanup();
 	MOV(32, R(RSCRATCH), PPCSTATE(pc));
 	MOV(32, PPCSTATE(npc), R(RSCRATCH));
-	ABI_PushRegistersAndAdjustStack(0, 0);
+	ABI_PushRegistersAndAdjustStack({}, 0);
 	ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExternalExceptions));
-	ABI_PopRegistersAndAdjustStack(0, 0);
+	ABI_PopRegistersAndAdjustStack({}, 0);
 	SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount));
 	JMP(asm_routines.dispatcher, true);
 }
@@ -565,9 +565,9 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 
 	if (ImHereDebug)
 	{
-		ABI_PushRegistersAndAdjustStack(0, 0);
+		ABI_PushRegistersAndAdjustStack({}, 0);
 		ABI_CallFunction((void *)&ImHere); //Used to get a trace of the last few blocks before a crash, sometimes VERY useful
-		ABI_PopRegistersAndAdjustStack(0, 0);
+		ABI_PopRegistersAndAdjustStack({}, 0);
 	}
 
 	// Conditionally add profiling code.
@@ -642,7 +642,7 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 		{
 			js.fifoBytesThisBlock -= 32;
 			MOV(32, PPCSTATE(pc), Imm32(jit->js.compilerPC)); // Helps external systems know which instruction triggered the write
-			u32 registersInUse = CallerSavedRegistersInUse();
+			BitSet32 registersInUse = CallerSavedRegistersInUse();
 			ABI_PushRegistersAndAdjustStack(registersInUse, 0);
 			ABI_CallFunction((void *)&GPFifo::CheckGatherPipe);
 			ABI_PopRegistersAndAdjustStack(registersInUse, 0);
@@ -727,9 +727,9 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 				fpr.Flush();
 
 				MOV(32, PPCSTATE(pc), Imm32(ops[i].address));
-				ABI_PushRegistersAndAdjustStack(0, 0);
+				ABI_PushRegistersAndAdjustStack({}, 0);
 				ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckBreakPoints));
-				ABI_PopRegistersAndAdjustStack(0, 0);
+				ABI_PopRegistersAndAdjustStack({}, 0);
 				TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));
 				FixupBranch noBreakpoint = J_CC(CC_Z);
 
@@ -744,29 +744,28 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 			// output, which needs to be bound in the actual instruction compilation.
 			// TODO: make this smarter in the case that we're actually register-starved, i.e.
 			// prioritize the more important registers.
-			for (int k = 0; k < 3 && gpr.NumFreeRegisters() >= 2; k++)
+			for (int reg : ops[i].regsIn)
 			{
-				int reg = ops[i].regsIn[k];
-				if (reg >= 0 && (ops[i].gprInReg & (1 << reg)) && !gpr.R(reg).IsImm())
+				if (gpr.NumFreeRegisters() < 2)
+					break;
+				if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm())
 					gpr.BindToRegister(reg, true, false);
 			}
-			for (int k = 0; k < 4 && fpr.NumFreeRegisters() >= 2; k++)
+			for (int reg : ops[i].regsOut)
 			{
-				int reg = ops[i].fregsIn[k];
-				if (reg >= 0 && (ops[i].fprInXmm & (1 << reg)))
-					fpr.BindToRegister(reg, true, false);
+				if (fpr.NumFreeRegisters() < 2)
+					break;
+				if (ops[i].fprInXmm[reg])
+					gpr.BindToRegister(reg, true, false);
 			}
 
 			Jit64Tables::CompileInstruction(ops[i]);
 
 			// If we have a register that will never be used again, flush it.
-			for (int j = 0; j < 32; j++)
-			{
-				if (!(ops[i].gprInUse & (1 << j)))
-					gpr.StoreFromRegister(j);
-				if (!(ops[i].fprInUse & (1 << j)))
-					fpr.StoreFromRegister(j);
-			}
+			for (int j : ~ops[i].gprInUse)
+				gpr.StoreFromRegister(j);
+			for (int j : ~ops[i].fprInUse)
+				fpr.StoreFromRegister(j);
 
 			if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
 			{
@@ -852,15 +851,15 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 	return normalEntry;
 }
 
-u32 Jit64::CallerSavedRegistersInUse()
+BitSet32 Jit64::CallerSavedRegistersInUse()
 {
-	u32 result = 0;
+	BitSet32 result;
 	for (int i = 0; i < NUMXREGS; i++)
 	{
 		if (!gpr.IsFreeX(i))
-			result |= (1 << i);
+			result[i] = true;
 		if (!fpr.IsFreeX(i))
-			result |= (1 << (16 + i));
+			result[16 + i] = true;
 	}
 	return result & ABI_ALL_CALLER_SAVED;
 }

Source/Core/Core/PowerPC/Jit64/Jit.h

@@ -78,7 +78,7 @@ public:
 	void Jit(u32 em_address) override;
 	const u8* DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buffer, JitBlock *b);
 
-	u32 CallerSavedRegistersInUse();
+	BitSet32 CallerSavedRegistersInUse();
 
 	JitBlockCache *GetBlockCache() override { return &blocks; }
 

Source/Core/Core/PowerPC/Jit64/JitAsm.cpp

@@ -43,9 +43,9 @@ void Jit64AsmRoutineManager::Generate()
 	MOV(64, R(RPPCSTATE), Imm64((u64)&PowerPC::ppcState + 0x80));
 
 	const u8* outerLoop = GetCodePtr();
-		ABI_PushRegistersAndAdjustStack(0, 0);
+		ABI_PushRegistersAndAdjustStack({}, 0);
 		ABI_CallFunction(reinterpret_cast<void *>(&CoreTiming::Advance));
-		ABI_PopRegistersAndAdjustStack(0, 0);
+		ABI_PopRegistersAndAdjustStack({}, 0);
 		FixupBranch skipToRealDispatch = J(SConfig::GetInstance().m_LocalCoreStartupParameter.bEnableDebugging); //skip the sync and compare first time
 		dispatcherMispredictedBLR = GetCodePtr();
 
@@ -71,9 +71,9 @@ void Jit64AsmRoutineManager::Generate()
 			{
 				TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(PowerPC::CPU_STEPPING));
 				FixupBranch notStepping = J_CC(CC_Z);
-				ABI_PushRegistersAndAdjustStack(0, 0);
+				ABI_PushRegistersAndAdjustStack({}, 0);
 				ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckBreakPoints));
-				ABI_PopRegistersAndAdjustStack(0, 0);
+				ABI_PopRegistersAndAdjustStack({}, 0);
 				TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));
 				dbg_exit = J_CC(CC_NZ, true);
 				SetJumpTarget(notStepping);
@@ -129,9 +129,9 @@ void Jit64AsmRoutineManager::Generate()
 			SetJumpTarget(notfound);
 
 			//Ok, no block, let's jit
-			ABI_PushRegistersAndAdjustStack(0, 0);
+			ABI_PushRegistersAndAdjustStack({}, 0);
 			ABI_CallFunctionA((void *)&Jit, PPCSTATE(pc));
-			ABI_PopRegistersAndAdjustStack(0, 0);
+			ABI_PopRegistersAndAdjustStack({}, 0);
 
 			// Jit might have cleared the code cache
 			ResetStack();
@@ -146,9 +146,9 @@ void Jit64AsmRoutineManager::Generate()
 		FixupBranch noExtException = J_CC(CC_Z);
 		MOV(32, R(RSCRATCH), PPCSTATE(pc));
 		MOV(32, PPCSTATE(npc), R(RSCRATCH));
-		ABI_PushRegistersAndAdjustStack(0, 0);
+		ABI_PushRegistersAndAdjustStack({}, 0);
 		ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExternalExceptions));
-		ABI_PopRegistersAndAdjustStack(0, 0);
+		ABI_PopRegistersAndAdjustStack({}, 0);
 		SetJumpTarget(noExtException);
 
 		TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));

Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp

@@ -95,42 +95,38 @@ void RegCache::UnlockAllX()
 		xreg.locked = false;
 }
 
-u32 GPRRegCache::GetRegUtilization()
+BitSet32 GPRRegCache::GetRegUtilization()
 {
 	return jit->js.op->gprInReg;
 }
 
-u32 FPURegCache::GetRegUtilization()
+BitSet32 FPURegCache::GetRegUtilization()
 {
 	return jit->js.op->gprInReg;
 }
 
-u32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
+BitSet32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
 {
-	u32 regsUsed = 0;
+	BitSet32 regsUsed;
 	for (u32 i = 1; i < lookahead; i++)
 	{
-		for (int j = 0; j < 3; j++)
-			if (jit->js.op[i].regsIn[j] >= 0)
-				regsUsed |= 1 << jit->js.op[i].regsIn[j];
-		for (int j = 0; j < 3; j++)
-			if ((size_t)jit->js.op[i].regsIn[j] == preg)
-				return regsUsed;
+		BitSet32 regsIn = jit->js.op[i].regsIn;
+		regsUsed |= regsIn;
+		if (regsIn[preg])
+			return regsUsed;
 	}
 	return regsUsed;
 }
 
-u32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
+BitSet32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
 {
-	u32 regsUsed = 0;
+	BitSet32 regsUsed;
 	for (u32 i = 1; i < lookahead; i++)
 	{
-		for (int j = 0; j < 4; j++)
-			if (jit->js.op[i].fregsIn[j] >= 0)
-				regsUsed |= 1 << jit->js.op[i].fregsIn[j];
-		for (int j = 0; j < 4; j++)
-			if ((size_t)jit->js.op[i].fregsIn[j] == preg)
-				return regsUsed;
+		BitSet32 regsIn = jit->js.op[i].fregsIn;
+		regsUsed |= regsIn;
+		if (regsIn[preg])
+			return regsUsed;
 	}
 	return regsUsed;
 }
@@ -151,17 +147,14 @@ float RegCache::ScoreRegister(X64Reg xr)
 
 	// If the register isn't actually needed in a physical register for a later instruction,
 	// writing it back to the register file isn't quite as bad.
-	if (GetRegUtilization() & (1 << preg))
+	if (GetRegUtilization()[preg])
 	{
 		// Don't look too far ahead; we don't want to have quadratic compilation times for
 		// enormous block sizes!
 		// This actually improves register allocation a tiny bit; I'm not sure why.
 		u32 lookahead = std::min(jit->js.instructionsLeft, 64);
 		// Count how many other registers are going to be used before we need this one again.
-		u32 regs_in = CountRegsIn(preg, lookahead);
-		u32 regs_in_count = 0;
-		for (int i = 0; i < 32; i++)
-			regs_in_count += !!(regs_in & (1 << i));
+		u32 regs_in_count = CountRegsIn(preg, lookahead).Count();
 		// Totally ad-hoc heuristic to bias based on how many other registers we'll need
 		// before this one gets used again.
 		score += 1 + 2 * (5 - log2f(1 + (float)regs_in_count));

Source/Core/Core/PowerPC/Jit64/JitRegCache.h

@@ -44,8 +44,8 @@ protected:
 
 	virtual const int *GetAllocationOrder(size_t& count) = 0;
 
-	virtual u32 GetRegUtilization() = 0;
-	virtual u32 CountRegsIn(size_t preg, u32 lookahead) = 0;
+	virtual BitSet32 GetRegUtilization() = 0;
+	virtual BitSet32 CountRegsIn(size_t preg, u32 lookahead) = 0;
 
 	Gen::XEmitter *emit;
 
@@ -137,8 +137,8 @@ public:
 	Gen::OpArg GetDefaultLocation(size_t reg) const override;
 	const int* GetAllocationOrder(size_t& count) override;
 	void SetImmediate32(size_t preg, u32 immValue);
-	u32 GetRegUtilization();
-	u32 CountRegsIn(size_t preg, u32 lookahead);
+	BitSet32 GetRegUtilization() override;
+	BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
 };
 
 
@@ -149,6 +149,6 @@ public:
 	void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
 	const int* GetAllocationOrder(size_t& count) override;
 	Gen::OpArg GetDefaultLocation(size_t reg) const override;
-	u32 GetRegUtilization();
-	u32 CountRegsIn(size_t preg, u32 lookahead);
+	BitSet32 GetRegUtilization() override;
+	BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
 };

Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp

@@ -134,7 +134,7 @@ void Jit64::lXXx(UGeckoInstruction inst)
 		TEST(32, gpr.R(d), gpr.R(d));
 		FixupBranch noIdle = J_CC(CC_NZ);
 
-		u32 registersInUse = CallerSavedRegistersInUse();
+		BitSet32 registersInUse = CallerSavedRegistersInUse();
 		ABI_PushRegistersAndAdjustStack(registersInUse, 0);
 
 		ABI_CallFunctionC((void *)&PowerPC::OnIdle, PowerPC::ppcState.gpr[a] + (s32)(s16)inst.SIMM_16);
@@ -246,11 +246,11 @@ void Jit64::lXXx(UGeckoInstruction inst)
 
 	gpr.Lock(a, b, d);
 	gpr.BindToRegister(d, js.memcheck, true);
-	u32 registersInUse = CallerSavedRegistersInUse();
+	BitSet32 registersInUse = CallerSavedRegistersInUse();
 	if (update && storeAddress)
 	{
 		// We need to save the (usually scratch) address register for the update.
-		registersInUse |= (1 << RSCRATCH2);
+		registersInUse[RSCRATCH2] = true;
 	}
 	SafeLoadToReg(gpr.RX(d), opAddress, accessSize, loadOffset, registersInUse, signExtend);
 
@@ -314,7 +314,7 @@ void Jit64::dcbz(UGeckoInstruction inst)
 	SwitchToFarCode();
 	SetJumpTarget(slow);
 	MOV(32, M(&PC), Imm32(jit->js.compilerPC));
-	u32 registersInUse = CallerSavedRegistersInUse();
+	BitSet32 registersInUse = CallerSavedRegistersInUse();
 	ABI_PushRegistersAndAdjustStack(registersInUse, 0);
 	ABI_CallFunctionR((void *)&Memory::ClearCacheLine, RSCRATCH);
 	ABI_PopRegistersAndAdjustStack(registersInUse, 0);
@@ -403,7 +403,7 @@ void Jit64::stX(UGeckoInstruction inst)
 				// Helps external systems know which instruction triggered the write
 				MOV(32, PPCSTATE(pc), Imm32(jit->js.compilerPC));
 
-				u32 registersInUse = CallerSavedRegistersInUse();
+				BitSet32 registersInUse = CallerSavedRegistersInUse();
 				ABI_PushRegistersAndAdjustStack(registersInUse, 0);
 				switch (accessSize)
 				{
@@ -555,7 +555,7 @@ void Jit64::lmw(UGeckoInstruction inst)
 		ADD(32, R(RSCRATCH2), gpr.R(inst.RA));
 	for (int i = inst.RD; i < 32; i++)
 	{
-		SafeLoadToReg(RSCRATCH, R(RSCRATCH2), 32, (i - inst.RD) * 4, CallerSavedRegistersInUse() | (1 << RSCRATCH_EXTRA), false);
+		SafeLoadToReg(RSCRATCH, R(RSCRATCH2), 32, (i - inst.RD) * 4, CallerSavedRegistersInUse() | BitSet32 { RSCRATCH_EXTRA }, false);
 		gpr.BindToRegister(i, false, true);
 		MOV(32, gpr.R(i), R(RSCRATCH));
 	}

Source/Core/Core/PowerPC/Jit64/Jit_LoadStoreFloating.cpp

@@ -65,9 +65,9 @@ void Jit64::lfXXX(UGeckoInstruction inst)
 			offset = (s16)inst.SIMM_16;
 	}
 
-	u32 registersInUse = CallerSavedRegistersInUse();
+	BitSet32 registersInUse = CallerSavedRegistersInUse();
 	if (update && js.memcheck)
-		registersInUse |= (1 << RSCRATCH2);
+		registersInUse[RSCRATCH2] = true;
 	SafeLoadToReg(RSCRATCH, addr, single ? 32 : 64, offset, registersInUse, false);
 	fpr.Lock(d);
 	fpr.BindToRegister(d, js.memcheck || !single);

Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp

@@ -26,6 +26,7 @@ The register allocation is linear scan allocation.
 
 #include <algorithm>
 
+#include "Common/BitSet.h"
 #include "Common/CPUDetect.h"
 #include "Common/MathUtil.h"
 #include "Core/HW/ProcessorInterface.h"
@@ -60,15 +61,15 @@ struct RegInfo
 		RegInfo(RegInfo&); // DO NOT IMPLEMENT
 };
 
-static u32 regsInUse(RegInfo& R)
+static BitSet32 regsInUse(RegInfo& R)
 {
-	u32 result = 0;
+	BitSet32 result;
 	for (unsigned i = 0; i < MAX_NUMBER_OF_REGS; i++)
 	{
 		if (R.regs[i] != nullptr)
-			result |= (1 << i);
+			result[i] = true;
 		if (R.fregs[i] != nullptr)
-			result |= (1 << (16 + i));
+			result[16 + i] = true;
 	}
 	return result;
 }

Source/Core/Core/PowerPC/JitCommon/JitAsmCommon.cpp

@@ -10,14 +10,11 @@
 #include "Core/PowerPC/JitCommon/JitBase.h"
 
 #define QUANTIZED_REGS_TO_SAVE \
-	(ABI_ALL_CALLER_SAVED & ~(\
-		(1 << RSCRATCH) | \
-		(1 << RSCRATCH2) | \
-		(1 << RSCRATCH_EXTRA)| \
-		(1 << (XMM0+16)) | \
-		(1 << (XMM1+16))))
+	(ABI_ALL_CALLER_SAVED & ~BitSet32 { \
+		RSCRATCH, RSCRATCH2, RSCRATCH_EXTRA, XMM0+16, XMM1+16 \
+	})
 
-#define QUANTIZED_REGS_TO_SAVE_LOAD (QUANTIZED_REGS_TO_SAVE | (1 << RSCRATCH2))
+#define QUANTIZED_REGS_TO_SAVE_LOAD (QUANTIZED_REGS_TO_SAVE | BitSet32 { RSCRATCH2 })
 
 using namespace Gen;
 

Source/Core/Core/PowerPC/JitCommon/JitBackpatch.cpp

@@ -72,7 +72,7 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
 		return false;
 	}
 
-	u32 registersInUse = it->second;
+	BitSet32 registersInUse = it->second;
 
 	if (!info.isMemoryWrite)
 	{
@@ -98,14 +98,14 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
 	else
 	{
 		// TODO: special case FIFO writes. Also, support 32-bit mode.
-		it = pcAtLoc.find(codePtr);
-		if (it == pcAtLoc.end())
+		auto it2 = pcAtLoc.find(codePtr);
+		if (it2 == pcAtLoc.end())
 		{
 			PanicAlert("BackPatch: no pc entry for address %p", codePtr);
 			return nullptr;
 		}
 
-		u32 pc = it->second;
+		u32 pc = it2->second;
 
 		u8 *start;
 		if (info.byteSwap || info.hasImmediate)

Source/Core/Core/PowerPC/JitCommon/Jit_Util.cpp

@@ -137,7 +137,7 @@ template <typename T>
 class MMIOReadCodeGenerator : public MMIO::ReadHandlingMethodVisitor<T>
 {
 public:
-	MMIOReadCodeGenerator(Gen::X64CodeBlock* code, u32 registers_in_use,
+	MMIOReadCodeGenerator(Gen::X64CodeBlock* code, BitSet32 registers_in_use,
 	                      Gen::X64Reg dst_reg, u32 address, bool sign_extend)
 		: m_code(code), m_registers_in_use(registers_in_use), m_dst_reg(dst_reg),
 		  m_address(address), m_sign_extend(sign_extend)
@@ -214,14 +214,14 @@ private:
 	}
 
 	Gen::X64CodeBlock* m_code;
-	u32 m_registers_in_use;
+	BitSet32 m_registers_in_use;
 	Gen::X64Reg m_dst_reg;
 	u32 m_address;
 	bool m_sign_extend;
 };
 
 void EmuCodeBlock::MMIOLoadToReg(MMIO::Mapping* mmio, Gen::X64Reg reg_value,
-                                 u32 registers_in_use, u32 address,
+                                 BitSet32 registers_in_use, u32 address,
                                  int access_size, bool sign_extend)
 {
 	switch (access_size)
@@ -250,17 +250,17 @@ void EmuCodeBlock::MMIOLoadToReg(MMIO::Mapping* mmio, Gen::X64Reg reg_value,
 	}
 }
 
-FixupBranch EmuCodeBlock::CheckIfSafeAddress(OpArg reg_value, X64Reg reg_addr, u32 registers_in_use, u32 mem_mask)
+FixupBranch EmuCodeBlock::CheckIfSafeAddress(OpArg reg_value, X64Reg reg_addr, BitSet32 registers_in_use, u32 mem_mask)
 {
-	registers_in_use |= (1 << reg_addr);
+	registers_in_use[reg_addr] = true;
 	if (reg_value.IsSimpleReg())
-		registers_in_use |= (1 << reg_value.GetSimpleReg());
+		registers_in_use[reg_value.GetSimpleReg()] = true;
 
 	// Get ourselves a free register; try to pick one that doesn't involve pushing, if we can.
 	X64Reg scratch = RSCRATCH;
-	if (!(registers_in_use & (1 << RSCRATCH)))
+	if (!registers_in_use[RSCRATCH])
 		scratch = RSCRATCH;
-	else if (!(registers_in_use & (1 << RSCRATCH_EXTRA)))
+	else if (!registers_in_use[RSCRATCH_EXTRA])
 		scratch = RSCRATCH_EXTRA;
 	else
 		scratch = reg_addr;
@@ -290,11 +290,11 @@ FixupBranch EmuCodeBlock::CheckIfSafeAddress(OpArg reg_value, X64Reg reg_addr, u
 	}
 }
 
-void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg & opAddress, int accessSize, s32 offset, u32 registersInUse, bool signExtend, int flags)
+void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg & opAddress, int accessSize, s32 offset, BitSet32 registersInUse, bool signExtend, int flags)
 {
 	if (!jit->js.memcheck)
 	{
-		registersInUse &= ~(1 << reg_value);
+		registersInUse[reg_value] = false;
 	}
 	if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU &&
 	    SConfig::GetInstance().m_LocalCoreStartupParameter.bFastmem &&
@@ -461,7 +461,7 @@ u8 *EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acce
 	return result;
 }
 
-void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags)
+void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset, BitSet32 registersInUse, int flags)
 {
 	// set the correct immediate format
 	if (reg_value.IsImm())
@@ -566,7 +566,7 @@ void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acces
 }
 
 // Destroys the same as SafeWrite plus RSCRATCH.  TODO: see if we can avoid temporaries here
-void EmuCodeBlock::SafeWriteF32ToReg(X64Reg xmm_value, X64Reg reg_addr, s32 offset, u32 registersInUse, int flags)
+void EmuCodeBlock::SafeWriteF32ToReg(X64Reg xmm_value, X64Reg reg_addr, s32 offset, BitSet32 registersInUse, int flags)
 {
 	// TODO: PSHUFB might be faster if fastmem supported MOVSS.
 	MOVD_xmm(R(RSCRATCH), xmm_value);

Source/Core/Core/PowerPC/JitCommon/Jit_Util.h

@@ -6,6 +6,7 @@
 
 #include <unordered_map>
 
+#include "Common/BitSet.h"
 #include "Common/CPUDetect.h"
 #include "Common/x64Emitter.h"
 
@@ -76,7 +77,7 @@ public:
 	void LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src);
 	void SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src);
 
-	Gen::FixupBranch CheckIfSafeAddress(Gen::OpArg reg_value, Gen::X64Reg reg_addr, u32 registers_in_use, u32 mem_mask);
+	Gen::FixupBranch CheckIfSafeAddress(Gen::OpArg reg_value, Gen::X64Reg reg_addr, BitSet32 registers_in_use, u32 mem_mask);
 	void UnsafeLoadRegToReg(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize, s32 offset = 0, bool signExtend = false);
 	void UnsafeLoadRegToRegNoSwap(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize, s32 offset, bool signExtend = false);
 	// these return the address of the MOV, for backpatching
@@ -89,7 +90,7 @@ public:
 
 	// Generate a load/write from the MMIO handler for a given address. Only
 	// call for known addresses in MMIO range (MMIO::IsMMIOAddress).
-	void MMIOLoadToReg(MMIO::Mapping* mmio, Gen::X64Reg reg_value, u32 registers_in_use, u32 address, int access_size, bool sign_extend);
+	void MMIOLoadToReg(MMIO::Mapping* mmio, Gen::X64Reg reg_value, BitSet32 registers_in_use, u32 address, int access_size, bool sign_extend);
 
 	enum SafeLoadStoreFlags
 	{
@@ -99,12 +100,12 @@ public:
 		SAFE_LOADSTORE_CLOBBER_RSCRATCH_INSTEAD_OF_ADDR = 8
 	};
 
-	void SafeLoadToReg(Gen::X64Reg reg_value, const Gen::OpArg & opAddress, int accessSize, s32 offset, u32 registersInUse, bool signExtend, int flags = 0);
+	void SafeLoadToReg(Gen::X64Reg reg_value, const Gen::OpArg & opAddress, int accessSize, s32 offset, BitSet32 registersInUse, bool signExtend, int flags = 0);
 	// Clobbers RSCRATCH or reg_addr depending on the relevant flag.  Preserves
 	// reg_value if the load fails and js.memcheck is enabled.
 	// Works with immediate inputs and simple registers only.
-	void SafeWriteRegToReg(Gen::OpArg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags = 0);
-	void SafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags = 0)
+	void SafeWriteRegToReg(Gen::OpArg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, BitSet32 registersInUse, int flags = 0);
+	void SafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, BitSet32 registersInUse, int flags = 0)
 	{
 		SafeWriteRegToReg(R(reg_value), reg_addr, accessSize, offset, registersInUse, flags);
 	}
@@ -115,7 +116,7 @@ public:
 		return swap && !cpu_info.bMOVBE && accessSize > 8;
 	}
 
-	void SafeWriteF32ToReg(Gen::X64Reg xmm_value, Gen::X64Reg reg_addr, s32 offset, u32 registersInUse, int flags = 0);
+	void SafeWriteF32ToReg(Gen::X64Reg xmm_value, Gen::X64Reg reg_addr, s32 offset, BitSet32 registersInUse, int flags = 0);
 
 	void WriteToConstRamAddress(int accessSize, Gen::X64Reg arg, u32 address, bool swap = false);
 	void JitGetAndClearCAOV(bool oe);
@@ -137,6 +138,6 @@ public:
 	void ConvertDoubleToSingle(Gen::X64Reg dst, Gen::X64Reg src);
 	void SetFPRF(Gen::X64Reg xmm);
 protected:
-	std::unordered_map<u8 *, u32> registersInUseAtLoc;
+	std::unordered_map<u8 *, BitSet32> registersInUseAtLoc;
 	std::unordered_map<u8 *, u32> pcAtLoc;
 };

Source/Core/Core/PowerPC/JitCommon/TrampolineCache.cpp

@@ -36,7 +36,7 @@ void TrampolineCache::Shutdown()
 	cachedTrampolines.clear();
 }
 
-const u8* TrampolineCache::GetReadTrampoline(const InstructionInfo &info, u32 registersInUse)
+const u8* TrampolineCache::GetReadTrampoline(const InstructionInfo &info, BitSet32 registersInUse)
 {
 	TrampolineCacheKey key = { registersInUse, 0, info };
 
@@ -49,7 +49,7 @@ const u8* TrampolineCache::GetReadTrampoline(const InstructionInfo &info, u32 re
 	return trampoline;
 }
 
-const u8* TrampolineCache::GenerateReadTrampoline(const InstructionInfo &info, u32 registersInUse)
+const u8* TrampolineCache::GenerateReadTrampoline(const InstructionInfo &info, BitSet32 registersInUse)
 {
 	if (GetSpaceLeft() < 1024)
 		PanicAlert("Trampoline cache full");
@@ -97,7 +97,7 @@ const u8* TrampolineCache::GenerateReadTrampoline(const InstructionInfo &info, u
 	return trampoline;
 }
 
-const u8* TrampolineCache::GetWriteTrampoline(const InstructionInfo &info, u32 registersInUse, u32 pc)
+const u8* TrampolineCache::GetWriteTrampoline(const InstructionInfo &info, BitSet32 registersInUse, u32 pc)
 {
 	TrampolineCacheKey key = { registersInUse, pc, info };
 
@@ -110,7 +110,7 @@ const u8* TrampolineCache::GetWriteTrampoline(const InstructionInfo &info, u32 r
 	return trampoline;
 }
 
-const u8* TrampolineCache::GenerateWriteTrampoline(const InstructionInfo &info, u32 registersInUse, u32 pc)
+const u8* TrampolineCache::GenerateWriteTrampoline(const InstructionInfo &info, BitSet32 registersInUse, u32 pc)
 {
 	if (GetSpaceLeft() < 1024)
 		PanicAlert("Trampoline cache full");
@@ -184,7 +184,7 @@ const u8* TrampolineCache::GenerateWriteTrampoline(const InstructionInfo &info,
 
 size_t TrampolineCacheKeyHasher::operator()(const TrampolineCacheKey& k) const
 {
-	size_t res = std::hash<int>()(k.registersInUse);
+	size_t res = std::hash<int>()(k.registersInUse.m_val);
 	res ^= std::hash<int>()(k.info.operandSize)    >> 1;
 	res ^= std::hash<int>()(k.info.regOperandReg)  >> 2;
 	res ^= std::hash<int>()(k.info.scaledReg)      >> 3;

Source/Core/Core/PowerPC/JitCommon/TrampolineCache.h

@@ -6,6 +6,7 @@
 
 #include <unordered_map>
 
+#include "Common/BitSet.h"
 #include "Common/CommonTypes.h"
 #include "Common/x64Analyzer.h"
 #include "Common/x64Emitter.h"
@@ -15,7 +16,7 @@ const int BACKPATCH_SIZE = 5;
 
 struct TrampolineCacheKey
 {
-	u32 registersInUse;
+	BitSet32 registersInUse;
 	u32 pc;
 	InstructionInfo info;
 
@@ -33,13 +34,13 @@ public:
 	void Init();
 	void Shutdown();
 
-	const u8* GetReadTrampoline(const InstructionInfo &info, u32 registersInUse);
-	const u8* GetWriteTrampoline(const InstructionInfo &info, u32 registersInUse, u32 pc);
+	const u8* GetReadTrampoline(const InstructionInfo &info, BitSet32 registersInUse);
+	const u8* GetWriteTrampoline(const InstructionInfo &info, BitSet32 registersInUse, u32 pc);
 	void ClearCodeSpace();
 
 private:
-	const u8* GenerateReadTrampoline(const InstructionInfo &info, u32 registersInUse);
-	const u8* GenerateWriteTrampoline(const InstructionInfo &info, u32 registersInUse, u32 pc);
+	const u8* GenerateReadTrampoline(const InstructionInfo &info, BitSet32 registersInUse);
+	const u8* GenerateWriteTrampoline(const InstructionInfo &info, BitSet32 registersInUse, u32 pc);
 
 	std::unordered_map<TrampolineCacheKey, const u8*, TrampolineCacheKeyHasher> cachedTrampolines;
 };

Source/Core/Core/PowerPC/PPCAnalyst.cpp

@@ -249,21 +249,15 @@ static bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b)
 	// That is, check that none of b's outputs matches any of a's inputs,
 	// and that none of a's outputs matches any of b's inputs.
 	// The latter does not apply if a is a cmp, of course, but doesn't hurt to check.
-	for (int j = 0; j < 3; j++)
-	{
-		int regInA = a.regsIn[j];
-		int regInB = b.regsIn[j];
-		// register collision: b outputs to one of a's inputs
-		if (regInA >= 0 && (b.regsOut[0] == regInA || b.regsOut[1] == regInA))
-			return false;
-		// register collision: a outputs to one of b's inputs
-		if (regInB >= 0 && (a.regsOut[0] == regInB || a.regsOut[1] == regInB))
-			return false;
-		// register collision: b outputs to one of a's outputs (overwriting it)
-		for (int k = 0; k < 2; k++)
-			if (b.regsOut[k] >= 0 && (b.regsOut[k] == a.regsOut[0] || b.regsOut[k] == a.regsOut[1]))
-				return false;
-	}
+	// register collision: b outputs to one of a's inputs
+	if (b.regsOut & a.regsIn)
+		return false;
+	// register collision: a outputs to one of b's inputs
+	if (a.regsOut & b.regsIn)
+		return false;
+	// register collision: b outputs to one of a's outputs (overwriting it)
+	if (b.regsOut & a.regsOut)
+		return false;
 
 	return true;
 }
@@ -520,42 +514,41 @@ void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInf
 	if (code->inst.OPCD == 31 && code->inst.SUBOP10 == 467) // mtspr
 		code->outputCA = ((code->inst.SPRU << 5) | (code->inst.SPRL & 0x1F)) == SPR_XER;
 
-	int numOut = 0;
-	int numIn = 0;
-	int numFloatIn = 0;
+	code->regsIn = BitSet32(0);
+	code->regsOut = BitSet32(0);
 	if (opinfo->flags & FL_OUT_A)
 	{
-		code->regsOut[numOut++] = code->inst.RA;
+		code->regsOut[code->inst.RA] = true;
 		block->m_gpa->SetOutputRegister(code->inst.RA, index);
 	}
 	if (opinfo->flags & FL_OUT_D)
 	{
-		code->regsOut[numOut++] = code->inst.RD;
+		code->regsOut[code->inst.RD] = true;
 		block->m_gpa->SetOutputRegister(code->inst.RD, index);
 	}
 	if (opinfo->flags & FL_OUT_S)
 	{
-		code->regsOut[numOut++] = code->inst.RS;
+		code->regsOut[code->inst.RS] = true;
 		block->m_gpa->SetOutputRegister(code->inst.RS, index);
 	}
 	if ((opinfo->flags & FL_IN_A) || ((opinfo->flags & FL_IN_A0) && code->inst.RA != 0))
 	{
-		code->regsIn[numIn++] = code->inst.RA;
+		code->regsIn[code->inst.RA] = true;
 		block->m_gpa->SetInputRegister(code->inst.RA, index);
 	}
 	if (opinfo->flags & FL_IN_B)
 	{
-		code->regsIn[numIn++] = code->inst.RB;
+		code->regsIn[code->inst.RB] = true;
 		block->m_gpa->SetInputRegister(code->inst.RB, index);
 	}
 	if (opinfo->flags & FL_IN_C)
 	{
-		code->regsIn[numIn++] = code->inst.RC;
+		code->regsIn[code->inst.RC] = true;
 		block->m_gpa->SetInputRegister(code->inst.RC, index);
 	}
 	if (opinfo->flags & FL_IN_S)
 	{
-		code->regsIn[numIn++] = code->inst.RS;
+		code->regsIn[code->inst.RS] = true;
 		block->m_gpa->SetInputRegister(code->inst.RS, index);
 	}
 
@@ -564,24 +557,17 @@ void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInf
 		code->fregOut = code->inst.FD;
 	else if (opinfo->flags & FL_OUT_FLOAT_S)
 		code->fregOut = code->inst.FS;
+	code->fregsIn = BitSet32(0);
 	if (opinfo->flags & FL_IN_FLOAT_A)
-		code->fregsIn[numFloatIn++] = code->inst.FA;
+		code->fregsIn[code->inst.FA] = true;
 	if (opinfo->flags & FL_IN_FLOAT_B)
-		code->fregsIn[numFloatIn++] = code->inst.FB;
+		code->fregsIn[code->inst.FB] = true;
 	if (opinfo->flags & FL_IN_FLOAT_C)
-		code->fregsIn[numFloatIn++] = code->inst.FC;
+		code->fregsIn[code->inst.FC] = true;
 	if (opinfo->flags & FL_IN_FLOAT_D)
-		code->fregsIn[numFloatIn++] = code->inst.FD;
+		code->fregsIn[code->inst.FD] = true;
 	if (opinfo->flags & FL_IN_FLOAT_S)
-		code->fregsIn[numFloatIn++] = code->inst.FS;
-
-	// Set remaining register slots as unused (-1)
-	for (int j = numIn; j < 3; j++)
-		code->regsIn[j] = -1;
-	for (int j = numOut; j < 2; j++)
-		code->regsOut[j] = -1;
-	for (int j = numFloatIn; j < 4; j++)
-		code->fregsIn[j] = -1;
+		code->fregsIn[code->inst.FS] = true;
 
 	switch (opinfo->type)
 	{
@@ -797,7 +783,7 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32
 	// Scan for flag dependencies; assume the next block (or any branch that can leave the block)
 	// wants flags, to be safe.
 	bool wantsCR0 = true, wantsCR1 = true, wantsFPRF = true, wantsCA = true;
-	u32 fprInUse = 0, gprInUse = 0, gprInReg = 0, fprInXmm = 0;
+	BitSet32 fprInUse, gprInUse, gprInReg, fprInXmm;
 	for (int i = block->m_num_instructions - 1; i >= 0; i--)
 	{
 		bool opWantsCR0 = code[i].wantsCR0;
@@ -822,30 +808,20 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32
 		code[i].fprInXmm = fprInXmm;
 		// TODO: if there's no possible endblocks or exceptions in between, tell the regcache
 		// we can throw away a register if it's going to be overwritten later.
-		for (int j = 0; j < 3; j++)
-			if (code[i].regsIn[j] >= 0)
-			{
-				gprInUse |= 1 << code[i].regsIn[j];
-				gprInReg |= 1 << code[i].regsIn[j];
-			}
-		for (int j = 0; j < 4; j++)
-			if (code[i].fregsIn[j] >= 0)
-			{
-				fprInUse |= 1 << code[i].fregsIn[j];
-				if (strncmp(code[i].opinfo->opname, "stfd", 4))
-					fprInXmm |= 1 << code[i].fregsIn[j];
-			}
+		gprInUse |= code[i].regsIn;
+		gprInReg |= code[i].regsIn;
+		fprInUse |= code[i].fregsIn;
+		if (strncmp(code[i].opinfo->opname, "stfd", 4))
+			fprInXmm |= code[i].fregsIn;
 		// For now, we need to count output registers as "used" though; otherwise the flush
 		// will result in a redundant store (e.g. store to regcache, then store again to
 		// the same location later).
-		for (int j = 0; j < 2; j++)
-			if (code[i].regsOut[j] >= 0)
-				gprInUse |= 1 << code[i].regsOut[j];
+		gprInUse |= code[i].regsOut;
 		if (code[i].fregOut >= 0)
 		{
-			fprInUse |= 1 << code[i].fregOut;
+			fprInUse[code[i].fregOut] = true;
 			if (strncmp(code[i].opinfo->opname, "stfd", 4))
-				fprInXmm |= 1 << code[i].fregOut;
+				fprInXmm[code[i].fregOut] = true;
 		}
 	}
 	return address;

Source/Core/Core/PowerPC/PPCAnalyst.h

@@ -10,6 +10,7 @@
 #include <string>
 #include <vector>
 
+#include "Common/BitSet.h"
 #include "Common/CommonTypes.h"
 #include "Core/PowerPC/PPCTables.h"
 
@@ -26,10 +27,10 @@ struct CodeOp //16B
 	u32 address;
 	u32 branchTo; //if 0, not a branch
 	int branchToIndex; //index of target block
-	s8 regsOut[2];
-	s8 regsIn[3];
+	BitSet32 regsOut;
+	BitSet32 regsIn;
+	BitSet32 fregsIn;
 	s8 fregOut;
-	s8 fregsIn[4];
 	bool isBranchTarget;
 	bool wantsCR0;
 	bool wantsCR1;
@@ -43,13 +44,13 @@ struct CodeOp //16B
 	bool canEndBlock;
 	bool skip;  // followed BL-s for example
 	// which registers are still needed after this instruction in this block
-	u32 fprInUse;
-	u32 gprInUse;
+	BitSet32 fprInUse;
+	BitSet32 gprInUse;
 	// just because a register is in use doesn't mean we actually need or want it in an x86 register.
-	u32 gprInReg;
+	BitSet32 gprInReg;
 	// we do double stores from GPRs, so we don't want to load a PowerPC floating point register into
 	// an XMM only to move it again to a GPR afterwards.
-	u32 fprInXmm;
+	BitSet32 fprInXmm;
 };
 
 struct BlockStats

Source/Core/Core/PowerPC/Profiler.h

@@ -23,7 +23,7 @@
 	MOV(64, M(pdt), R(RSCRATCH));
 
 #define PROFILER_VPUSH \
-	u32 registersInUse = CallerSavedRegistersInUse(); \
+	BitSet32 registersInUse = CallerSavedRegistersInUse(); \
 	ABI_PushRegistersAndAdjustStack(registersInUse, 0);
 
 #define PROFILER_VPOP \