From 2bae49bdad66bdc956352f9398ef1233e0f5528a Mon Sep 17 00:00:00 2001 From: Yaya48 Date: Tue, 13 Oct 2026 22:03:22 +0200 Subject: [PATCH] IOS LLE: the ARM926 TLB is unified (StarOS MMU-001 F1 review) The ARM926EJ-S has one TLB for instructions and data, with lockdown entries that whole-TLB invalidation preserves. Two comments said the I and D TLBs were separate; they now say what the software TLB really differs in: capacity and replacement (a direct-mapped cache of 4096 1 KiB granules), and lockdown, which is not modelled (c10 writes are ignored). No code change. Co-Authored-By: Claude Opus 5.5 --- Source/Core/Core/IOS/Starlet/ARMCore.cpp | 4 ++-- Source/Core/Core/IOS/Starlet/ARMCore.h | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Source/Core/Core/IOS/Starlet/ARMCore.cpp b/Source/Core/Core/IOS/Starlet/ARMCore.cpp index 3a65087326..4701b5dd7f 100644 --- a/Source/Core/Core/IOS/Starlet/ARMCore.cpp +++ b/Source/Core/Core/IOS/Starlet/ARMCore.cpp @@ -3130,8 +3130,8 @@ void ARMCore::WriteCP15(u32 opcode1, u32 crn, u32 crm, u32 opcode2, u32 value) InvalidateInstructionCache(); break; case 8: // TLB maintenance. - // With MMU faults, c8 c5/c6/c7 opcode2 1 invalidate the single entry that maps the MVA in Rd; - // the separate I and D TLBs share one software TLB, so each operation reaches both. + // With MMU faults, c8 c5/c6/c7 opcode2 1 invalidate the single entry that maps the MVA in Rd. + // The ARM926EJ-S TLB is unified, so the I, D and unified forms act on the same entries. if (m_mmu_faults && opcode2 == 1 && (crm == 5 || crm == 6 || crm == 7)) InvalidateTLBEntry(value); else diff --git a/Source/Core/Core/IOS/Starlet/ARMCore.h b/Source/Core/Core/IOS/Starlet/ARMCore.h index a457b4ec6e..b4cdc1ca13 100644 --- a/Source/Core/Core/IOS/Starlet/ARMCore.h +++ b/Source/Core/Core/IOS/Starlet/ARMCore.h @@ -399,9 +399,13 @@ private: u32 m_spsr_und = 0; CP15State m_cp15{}; - // ARM926 has separate instruction/data TLBs. A unified 1 KiB-granularity - // software cache keeps the observable translations while avoiding a - // page-table walk on every interpreted access. + // The ARM926EJ-S has one TLB for instructions and data: set-associative main entries plus + // lockdown entries (c10) that whole-TLB invalidation preserves (ARM926EJ-S TRM). This software + // TLB is unified too, but it is a 4096-entry direct-mapped cache of 1 KiB granules, so its + // capacity and replacement differ: an entry can stay here after the hardware would have + // replaced it, or be replaced here while the hardware keeps it. Lockdown is not modelled (c10 + // writes are ignored). It keeps the observable translations while avoiding a page-table walk on + // every interpreted access. mutable std::array m_tlb{}; std::array m_instruction_cache{}; mutable u32 m_tlb_generation = 1;