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Merge pull request #25 from Tilka/ppc_fp

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Fix non-IEEE mode
This commit is contained in:
Pierre Bourdon committed 2014-02-23 04:15:37 +01:00
2 parents f9ed70b2f9 ee21cbe2d1
commit 311caef094
10 files changed
+357 -57
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Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h
+35
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@@ -231,3 +231,38 @@ inline u32 ConvertToSingleFTZ(u64 x)
return (x >> 32) & 0x80000000;
}
}
inline u64 ConvertToDouble(u32 _x)
{
// This is a little-endian re-implementation of the algorithm described in
// the PowerPC Programming Environments Manual for loading single
// precision floating point numbers.
// See page 566 of http://www.freescale.com/files/product/doc/MPCFPE32B.pdf
u64 x = _x;
u64 exp = (x >> 23) & 0xff;
u64 frac = x & 0x007fffff;
if (exp > 0 && exp < 255) // Normal number
{
u64 y = !(exp >> 7);
u64 z = y << 61 | y << 60 | y << 59;
return ((x & 0xc0000000) << 32) | z | ((x & 0x3fffffff) << 29);
}
else if (exp == 0 && frac != 0) // Subnormal number
{
exp = 1023 - 126;
do
{
frac <<= 1;
exp -= 1;
} while ((frac & 0x00800000) == 0);
return ((x & 0x80000000) << 32) | (exp << 52) | ((frac & 0x007fffff) << 29);
}
else // QNaN, SNaN or Zero
{
u64 y = exp >> 7;
u64 z = y << 61 | y << 60 | y << 59;
return ((x & 0xc0000000) << 32) | z | ((x & 0x3fffffff) << 29);
}
}
Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
+12 -15
View File
@@ -92,9 +92,9 @@ void Interpreter::lfs(UGeckoInstruction _inst)
u32 uTemp = Memory::Read_U32(Helper_Get_EA(_inst));
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{
double value = *(float*)&uTemp;
rPS0(_inst.FD) = value;
rPS1(_inst.FD) = value;
u64 value = ConvertToDouble(uTemp);
riPS0(_inst.FD) = value;
riPS1(_inst.FD) = value;
}
}
@@ -104,9 +104,9 @@ void Interpreter::lfsu(UGeckoInstruction _inst)
u32 uTemp = Memory::Read_U32(uAddress);
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{
double value = *(float*)&uTemp;
rPS0(_inst.FD) = value;
rPS1(_inst.FD) = value;
u64 value = ConvertToDouble(uTemp);
riPS0(_inst.FD) = value;
riPS1(_inst.FD) = value;
m_GPR[_inst.RA] = uAddress;
}
@@ -118,9 +118,9 @@ void Interpreter::lfsux(UGeckoInstruction _inst)
u32 uTemp = Memory::Read_U32(uAddress);
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{
double value = *(float*)&uTemp;
rPS0(_inst.FD) = value;
rPS1(_inst.FD) = value;
u64 value = ConvertToDouble(uTemp);
riPS0(_inst.FD) = value;
riPS1(_inst.FD) = value;
m_GPR[_inst.RA] = uAddress;
}
}
@@ -130,9 +130,9 @@ void Interpreter::lfsx(UGeckoInstruction _inst)
u32 uTemp = Memory::Read_U32(Helper_Get_EA_X(_inst));
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{
double value = *(float*)&uTemp;
rPS0(_inst.FD) = value;
rPS1(_inst.FD) = value;
u64 value = ConvertToDouble(uTemp);
riPS0(_inst.FD) = value;
riPS1(_inst.FD) = value;
}
}
@@ -281,9 +281,6 @@ void Interpreter::stfdu(UGeckoInstruction _inst)
void Interpreter::stfs(UGeckoInstruction _inst)
{
//double value = rPS0(_inst.FS);
//float fTemp = (float)value;
//Memory::Write_U32(*(u32*)&fTemp, Helper_Get_EA(_inst));
Memory::Write_U32(ConvertToSingle(riPS0(_inst.FS)), Helper_Get_EA(_inst));
}
Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
+1 -1
View File
@@ -374,7 +374,7 @@ void RegCache::Flush(FlushMode mode)
{
if (locks[i])
{
PanicAlert("Someone forgot to unlock PPC reg %i.", i);
PanicAlert("Someone forgot to unlock PPC reg %i (X64 reg %i).", i, RX(i));
}
if (regs[i].away)
{
Source/Core/Core/PowerPC/Jit64/Jit_LoadStoreFloating.cpp
+21 -25
View File
@@ -12,6 +12,8 @@
#include "Core/PowerPC/Jit64/JitAsm.h"
#include "Core/PowerPC/Jit64/JitRegCache.h"
namespace {
// pshufb todo: MOVQ
const u8 GC_ALIGNED16(bswapShuffle1x4[16]) = {3, 2, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
const u8 GC_ALIGNED16(bswapShuffle2x4[16]) = {3, 2, 1, 0, 7, 6, 5, 4, 8, 9, 10, 11, 12, 13, 14, 15};
@@ -19,11 +21,10 @@ const u8 GC_ALIGNED16(bswapShuffle1x8[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 8, 9, 10,
const u8 GC_ALIGNED16(bswapShuffle1x8Dupe[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0};
const u8 GC_ALIGNED16(bswapShuffle2x8[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
namespace {
u64 GC_ALIGNED16(temp64);
u32 GC_ALIGNED16(temp32);
}
// TODO: Add peephole optimizations for multiple consecutive lfd/lfs/stfd/stfs since they are so common,
// and pshufb could help a lot.
// Also add hacks for things like lfs/stfs the same reg consecutively, that is, simple memory moves.
@@ -46,11 +47,9 @@ void Jit64::lfs(UGeckoInstruction inst)
MEMCHECK_START
MOV(32, M(&temp32), R(EAX));
fpr.Lock(d);
fpr.BindToRegister(d, false);
CVTSS2SD(fpr.RX(d), M(&temp32));
MOVDDUP(fpr.RX(d), fpr.R(d));
ConvertSingleToDouble(fpr.RX(d), EAX, true);
MEMCHECK_END
@@ -226,13 +225,15 @@ void Jit64::stfs(UGeckoInstruction inst)
return;
}
fpr.BindToRegister(s, true, false);
ConvertDoubleToSingle(XMM0, fpr.RX(s));
if (gpr.R(a).IsImm())
{
u32 addr = (u32)(gpr.R(a).offset + offset);
if (Memory::IsRAMAddress(addr))
{
if (cpu_info.bSSSE3) {
CVTSD2SS(XMM0, fpr.R(s));
PSHUFB(XMM0, M((void *)bswapShuffle1x4));
WriteFloatToConstRamAddress(XMM0, addr);
return;
@@ -241,7 +242,6 @@ void Jit64::stfs(UGeckoInstruction inst)
else if (addr == 0xCC008000)
{
// Float directly to write gather pipe! Fun!
CVTSD2SS(XMM0, fpr.R(s));
CALL((void*)asm_routines.fifoDirectWriteFloat);
// TODO
js.fifoBytesThisBlock += 4;
@@ -251,7 +251,6 @@ void Jit64::stfs(UGeckoInstruction inst)
gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
gpr.Lock(a);
fpr.Lock(s);
MOV(32, R(ABI_PARAM2), gpr.R(a));
ADD(32, R(ABI_PARAM2), Imm32(offset));
if (update && offset)
@@ -266,7 +265,6 @@ void Jit64::stfs(UGeckoInstruction inst)
MEMCHECK_END
}
CVTSD2SS(XMM0, fpr.R(s));
SafeWriteFloatToReg(XMM0, ABI_PARAM2, RegistersInUse());
gpr.UnlockAll();
gpr.UnlockAllX();
@@ -281,11 +279,14 @@ void Jit64::stfsx(UGeckoInstruction inst)
// We can take a shortcut here - it's not likely that a hardware access would use this instruction.
gpr.FlushLockX(ABI_PARAM1);
fpr.Lock(inst.RS);
MOV(32, R(ABI_PARAM1), gpr.R(inst.RB));
if (inst.RA)
ADD(32, R(ABI_PARAM1), gpr.R(inst.RA));
CVTSD2SS(XMM0, fpr.R(inst.RS));
int s = inst.RS;
fpr.Lock(s);
fpr.BindToRegister(s, true, false);
ConvertDoubleToSingle(XMM0, fpr.RX(s));
MOVD_xmm(R(EAX), XMM0);
SafeWriteRegToReg(EAX, ABI_PARAM1, 32, 0, RegistersInUse());
@@ -304,21 +305,20 @@ void Jit64::lfsx(UGeckoInstruction inst)
{
ADD(32, R(EAX), gpr.R(inst.RA));
}
fpr.Lock(inst.RS);
fpr.BindToRegister(inst.RS, false);
X64Reg s = fpr.RX(inst.RS);
if (cpu_info.bSSSE3 && !js.memcheck) {
fpr.Lock(inst.RS);
fpr.BindToRegister(inst.RS, false, true);
X64Reg r = fpr.R(inst.RS).GetSimpleReg();
#ifdef _M_IX86
AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
MOVD_xmm(r, MDisp(EAX, (u32)Memory::base));
MOVD_xmm(XMM0, MDisp(EAX, (u32)Memory::base));
#else
MOVD_xmm(r, MComplex(RBX, EAX, SCALE_1, 0));
MOVD_xmm(XMM0, MComplex(RBX, EAX, SCALE_1, 0));
#endif
MEMCHECK_START
PSHUFB(r, M((void *)bswapShuffle1x4));
CVTSS2SD(r, R(r));
MOVDDUP(r, R(r));
PSHUFB(XMM0, M((void *)bswapShuffle1x4));
ConvertSingleToDouble(s, XMM0);
MEMCHECK_END
} else {
@@ -326,11 +326,7 @@ void Jit64::lfsx(UGeckoInstruction inst)
MEMCHECK_START
MOV(32, M(&temp32), R(EAX));
CVTSS2SD(XMM0, M(&temp32));
fpr.Lock(inst.RS);
fpr.BindToRegister(inst.RS, false, true);
MOVDDUP(fpr.R(inst.RS).GetSimpleReg(), R(XMM0));
ConvertSingleToDouble(s, EAX, true);
MEMCHECK_END
}
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
+12 -7
View File
@@ -1290,10 +1290,12 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
}
case DupSingleToMReg: {
if (!thisUsed) break;
X64Reg reg = fregURegWithoutMov(RI, I);
Jit->CVTSS2SD(reg, fregLocForInst(RI, getOp1(I)));
Jit->MOVDDUP(reg, R(reg));
RI.fregs[reg] = I;
X64Reg input = fregEnsureInReg(RI, getOp1(I));
X64Reg output = fregURegWithoutMov(RI, I);
Jit->ConvertSingleToDouble(output, input);
RI.fregs[output] = I;
fregNormalRegClear(RI, I);
break;
}
@@ -1414,9 +1416,12 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
}
case DoubleToSingle: {
if (!thisUsed) break;
X64Reg reg = fregURegWithoutMov(RI, I);
Jit->CVTSD2SS(reg, fregLocForInst(RI, getOp1(I)));
RI.fregs[reg] = I;
X64Reg input = fregEnsureInReg(RI, getOp1(I));
X64Reg output = fregURegWithoutMov(RI, I);
Jit->ConvertDoubleToSingle(output, input);
RI.fregs[output] = I;
fregNormalRegClear(RI, I);
break;
}
Source/Core/Core/PowerPC/JitCommon/Jit_Util.cpp
+194
View File
@@ -416,6 +416,200 @@ void EmuCodeBlock::ForceSinglePrecisionP(X64Reg xmm) {
}
}
static u32 GC_ALIGNED16(temp32);
static u64 GC_ALIGNED16(temp64);
#ifdef _WIN32
#include <intrin.h>
#ifdef _M_X64
static const __m128i GC_ALIGNED16(single_qnan_bit) = _mm_set_epi64x(0, 0x0000000000400000);
static const __m128i GC_ALIGNED16(single_exponent) = _mm_set_epi64x(0, 0x000000007f800000);
static const __m128i GC_ALIGNED16(double_qnan_bit) = _mm_set_epi64x(0, 0x0008000000000000);
static const __m128i GC_ALIGNED16(double_exponent) = _mm_set_epi64x(0, 0x7ff0000000000000);
#else
static const __m128i GC_ALIGNED16(single_qnan_bit) = _mm_set_epi32(0, 0, 0x00000000, 0x00400000);
static const __m128i GC_ALIGNED16(single_exponent) = _mm_set_epi32(0, 0, 0x00000000, 0x7f800000);
static const __m128i GC_ALIGNED16(double_qnan_bit) = _mm_set_epi32(0, 0, 0x00080000, 0x00000000);
static const __m128i GC_ALIGNED16(double_exponent) = _mm_set_epi32(0, 0, 0x7ff00000, 0x00000000);
#endif
#else
static const __uint128_t GC_ALIGNED16(single_qnan_bit) = 0x0000000000400000;
static const __uint128_t GC_ALIGNED16(single_exponent) = 0x000000007f800000;
static const __uint128_t GC_ALIGNED16(double_qnan_bit) = 0x0008000000000000;
static const __uint128_t GC_ALIGNED16(double_exponent) = 0x7ff0000000000000;
#endif
// Since the following float conversion functions are used in non-arithmetic PPC float instructions,
// they must convert floats bitexact and never flush denormals to zero or turn SNaNs into QNaNs.
// This means we can't use CVTSS2SD/CVTSD2SS :(
// The x87 FPU doesn't even support flush-to-zero so we can use FLD+FSTP even on denormals.
// If the number is a NaN, make sure to set the QNaN bit back to its original value.
// Another problem is that officially, converting doubles to single format results in undefined behavior.
// Relying on undefined behavior is a bug so no software should ever do this.
// In case it does happen, phire's more accurate implementation of ConvertDoubleToSingle() is reproduced below.
//#define MORE_ACCURATE_DOUBLETOSINGLE
#ifdef MORE_ACCURATE_DOUBLETOSINGLE
#ifdef _WIN32
#ifdef _M_X64
static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi64x(0, 0x000fffffffffffff);
static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi64x(0, 0x8000000000000000);
static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi64x(0, 0x0010000000000000);
static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi64x(0, 0xc000000000000000);
static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi64x(0, 0x07ffffffe0000000);
#else
static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi32(0, 0, 0x000fffff, 0xffffffff);
static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi32(0, 0, 0x80000000, 0x00000000);
static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi32(0, 0, 0x00100000, 0x00000000);
static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi32(0, 0, 0xc0000000, 0x00000000);
static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi32(0, 0, 0x07ffffff, 0xe0000000);
#endif
#else
static const __uint128_t GC_ALIGNED16(double_fraction) = 0x000fffffffffffff;
static const __uint128_t GC_ALIGNED16(double_sign_bit) = 0x8000000000000000;
static const __uint128_t GC_ALIGNED16(double_explicit_top_bit) = 0x0010000000000000;
static const __uint128_t GC_ALIGNED16(double_top_two_bits) = 0xc000000000000000;
static const __uint128_t GC_ALIGNED16(double_bottom_bits) = 0x07ffffffe0000000;
#endif
// This is the same algorithm used in the interpreter (and actual hardware)
// The documentation states that the conversion of a double with an outside the
// valid range for a single (or a single denormal) is undefined.
// But testing on actual hardware shows it always picks bits 0..1 and 5..34
// unless the exponent is in the range of 874 to 896.
void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
{
MOVSD(XMM1, R(src));
// Grab Exponent
PAND(XMM1, M((void *)&double_exponent));
PSRLQ(XMM1, 52);
MOVD_xmm(R(EAX), XMM1);
// Check if the double is in the range of valid single subnormal
CMP(16, R(EAX), Imm16(896));
FixupBranch NoDenormalize = J_CC(CC_G);
CMP(16, R(EAX), Imm16(874));
FixupBranch NoDenormalize2 = J_CC(CC_L);
// Denormalise
// shift = (905 - Exponent) plus the 21 bit double to single shift
MOV(16, R(EAX), Imm16(905 + 21));
MOVD_xmm(XMM0, R(EAX));
PSUBQ(XMM0, R(XMM1));
// xmm1 = fraction | 0x0010000000000000
MOVSD(XMM1, R(src));
PAND(XMM1, M((void *)&double_fraction));
POR(XMM1, M((void *)&double_explicit_top_bit));
// fraction >> shift
PSRLQ(XMM1, R(XMM0));
// OR the sign bit in.
MOVSD(XMM0, R(src));
PAND(XMM0, M((void *)&double_sign_bit));
PSRLQ(XMM0, 32);
POR(XMM1, R(XMM0));
FixupBranch end = J(false); // Goto end
SetJumpTarget(NoDenormalize);
SetJumpTarget(NoDenormalize2);
// Don't Denormalize
// We want bits 0, 1
MOVSD(XMM1, R(src));
PAND(XMM1, M((void *)&double_top_two_bits));
PSRLQ(XMM1, 32);
// And 5 through to 34
MOVSD(XMM0, R(src));
PAND(XMM0, M((void *)&double_bottom_bits));
PSRLQ(XMM0, 29);
// OR them togther
POR(XMM1, R(XMM0));
// End
SetJumpTarget(end);
MOVDDUP(dst, R(XMM1));
}
#else // MORE_ACCURATE_DOUBLETOSINGLE
void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
{
MOVSD(M(&temp64), src);
MOVSD(XMM1, R(src));
FLD(64, M(&temp64));
CCFlags cond;
if (cpu_info.bSSE4_1) {
PTEST(XMM1, M((void *)&double_exponent));
cond = CC_NC;
} else {
FNSTSW_AX();
TEST(16, R(AX), Imm16(x87_InvalidOperation));
cond = CC_Z;
}
FSTP(32, M(&temp32));
MOVSS(XMM0, M(&temp32));
FixupBranch dont_reset_qnan_bit = J_CC(cond);
PANDN(XMM1, M((void *)&double_qnan_bit));
PSRLQ(XMM1, 29);
if (cpu_info.bAVX) {
VPANDN(XMM0, XMM1, R(XMM0));
} else {
PANDN(XMM1, R(XMM0));
MOVSS(XMM0, R(XMM1));
}
SetJumpTarget(dont_reset_qnan_bit);
MOVDDUP(dst, R(XMM0));
}
#endif // MORE_ACCURATE_DOUBLETOSINGLE
void EmuCodeBlock::ConvertSingleToDouble(X64Reg dst, X64Reg src, bool src_is_gpr)
{
if (src_is_gpr) {
MOV(32, M(&temp32), R(src));
MOVD_xmm(XMM1, R(src));
} else {
MOVSS(M(&temp32), src);
MOVSS(R(XMM1), src);
}
FLD(32, M(&temp32));
CCFlags cond;
if (cpu_info.bSSE4_1) {
PTEST(XMM1, M((void *)&single_exponent));
cond = CC_NC;
} else {
FNSTSW_AX();
TEST(16, R(AX), Imm16(x87_InvalidOperation));
cond = CC_Z;
}
FSTP(64, M(&temp64));
MOVSD(dst, M(&temp64));
FixupBranch dont_reset_qnan_bit = J_CC(cond);
PANDN(XMM1, M((void *)&single_qnan_bit));
PSLLQ(XMM1, 29);
if (cpu_info.bAVX) {
VPANDN(dst, XMM1, R(dst));
} else {
PANDN(XMM1, R(dst));
MOVSD(dst, R(XMM1));
}
SetJumpTarget(dont_reset_qnan_bit);
MOVDDUP(dst, R(dst));
}
void EmuCodeBlock::JitClearCA()
{
AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(~XER_CA_MASK)); //XER.CA = 0
Source/Core/Core/PowerPC/JitCommon/Jit_Util.h
+4
View File
@@ -48,6 +48,10 @@ public:
void ForceSinglePrecisionS(Gen::X64Reg xmm);
void ForceSinglePrecisionP(Gen::X64Reg xmm);
// AX might get trashed
void ConvertSingleToDouble(Gen::X64Reg dst, Gen::X64Reg src, bool src_is_gpr = false);
void ConvertDoubleToSingle(Gen::X64Reg dst, Gen::X64Reg src);
protected:
std::unordered_map<u8 *, u32> registersInUseAtLoc;
};